Question

我正在尝试使用VHDL制作数字时钟，我想在VGA屏幕上显示结果。但我坚持认为如何将整数类型转换为BCD？因为现在我将小时，分钟和秒数据作为整数得到，我将实现它，以便我可以以最充分的方式在我的VGA组件中使用它。你对此提出了什么建议？

提前致谢！

Answer 1

“以最充足（高效？）的方式实施”是什么意思？你的意思是不使用32位X 3来存储时间吗？

是否必须使用BCD？您可以限制整数的大小：小时为5位，分钟为6位，第二位为6位：

SIGNAL hour: INTEGER RANGE 0 TO 23;
SIGNAL minute: INTEGER RANGE 0 TO 59;
SIGNAL second: INTEGER RANGE 0 TO 59;

如果它们都需要在一个变量中，你可以将它们全部放入17位的位向量中。

SIGNAL time: BIT_VECTOR( 16 DOWNTO 0 );
time( 16 DOWNTO 12) <= hour;
time( 11 DOWNTO 6) <= minute;
time( 5 DOWNTO 0) <= second;

Answer 2

如果你想分开定时器，你可以使用除法和模运算符将整数转换为BCD。然而，这很可能合成得相当糟糕。您可能只需实现六个计数器，如下所示：

library ieee;
use ieee.std_logic_1164.all;

entity clock is
        port (
                resetAX : in std_logic; -- Asynchronous reset, active low
                clk : in std_logic;  -- Clock signal, runs faster than 1/second
                second_enable : in std_logic; -- Signal active (high) only when seconds to be incremented
                h_ms : out std_logic_vector(1 downto 0); -- MS digit of hour (0, 1, 2)
                h_ls : out std_logic_vector(3 downto 0); -- LS digit of hour (0-9)
                m_ms : out std_logic_vector(2 downto 0); -- MS digit of minute (0-5)
                m_ls : out std_logic_vector(3 downto 0); -- LS digit of minute (0-9)
                s_ms : out std_logic_vector(2 downto 0); -- MS digit of second (0-5)
                s_ls : out std_logic_vector(3 downto 0)  -- LS digit of second (0-9)
        );
end clock;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

architecture rtl of clock is
        signal h_ms_int : integer range 0 to 2;
        signal h_ls_int : integer range 0 to 9;
        signal m_ms_int : integer range 0 to 5;
        signal m_ls_int : integer range 0 to 9;
        signal s_ms_int : integer range 0 to 5;
        signal s_ls_int : integer range 0 to 9;
begin

        COUNT: process(resetAX, clk)
        begin
                if resetAX = '0' then
                        h_ms_int <= 0;
                        h_ls_int <= 0;
                        m_ms_int <= 0;
                        m_ls_int <= 0;
                        s_ms_int <= 0;
                        s_ls_int <= 0;
                elsif clk'event and clk='1' then
                        if second_enable = '1' then
                                if s_ls_int = 9 then
                                        if s_ms_int = 5 then
                                                if m_ls_int = 9 then
                                                        if m_ms_int = 5 then
                                                                if (h_ls_int = 9 or (h_ls_int=3 and h_ms_int=2)) then
                                                                        if (h_ls_int=3 and h_ms_int=2) then
                                                                                h_ms_int <= 0;
                                                                        else
                                                                                h_ms_int <= h_ms_int + 1;
                                                                        end if;
                                                                        h_ls_int <= 0;
                                                                else
                                                                        h_ls_int <= h_ls_int + 1;
                                                                end if;
                                                                m_ms_int <= 0;
                                                        else
                                                                m_ms_int <= m_ms_int + 1;
                                                        end if;
                                                        m_ls_int <= 0;
                                                else
                                                        m_ls_int <= m_ls_int + 1;
                                                end if;
                                                s_ms_int <= 0;
                                        else
                                                s_ms_int <= s_ms_int + 1;
                                        end if;
                                        s_ls_int <= 0;
                                else
                                        s_ls_int <= s_ls_int + 1;
                                end if;
                        end if;
                end if;
        end process COUNT;

        h_ms <= std_logic_vector(to_unsigned(h_ms_int, h_ms'length));
        h_ls <= std_logic_vector(to_unsigned(h_ls_int, h_ls'length));
        m_ms <= std_logic_vector(to_unsigned(m_ms_int, m_ms'length));
        m_ls <= std_logic_vector(to_unsigned(m_ls_int, m_ls'length));
        s_ms <= std_logic_vector(to_unsigned(s_ms_int, s_ms'length));
        s_ls <= std_logic_vector(to_unsigned(s_ls_int, s_ls'length));

end rtl;

这些是非常小的计数器，所以即使使用稍微复杂的包装逻辑也不应该太大。我无法在家检查它的大小，因为我这里没有任何合成工具，但我希望它应该小于十分和模十逻辑。

用VHDL实现数字时钟

2 个答案: