Question

我正在研究VHDL以获取我的学位，并要求我修复此代码中的错误，但是经过多次尝试，我无法设法使其运行。编译器返回“ Mem_Addr已使用但未声明”，突出显示了我在下面提到的那一行。我无法正确声明Mem_Addr。

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.ALL;
ENTITY Ifetch IS
PORT( SIGNAL Instruction : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL PC_plus_4_out : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 );
SIGNAL Add_result : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 );
SIGNAL Branch : IN STD_LOGIC;
SIGNAL Zero : IN STD_LOGIC;
SIGNAL PC_out : OUT STD_LOGIC_VECTOR( 9 DOWNTO 0 );
SIGNAL clock, reset : IN STD_LOGIC);
END Ifetch;
ARCHITECTURE behavior OF Ifetch IS
SIGNAL PC, PC_plus_4 : STD_LOGIC_VECTOR( 9 DOWNTO 0 );
SIGNAL next_PC : STD_LOGIC_VECTOR( 7 DOWNTO 0 );
BEGIN
--ROM for Instruction Memory
data_memory: altsyncram
GENERIC MAP (
operation_mode => "ROM",
width_a => 32,
widthad_a => 8,
lpm_type => "altsyncram",
outdata_reg_a => "UNREGISTERED",
-- Reads in mif file for initial data memory values
init_file => "program.mif",
intended_device_family => "Cyclone")
-- Fetch next instruction from memory using PC
PORT MAP (
clock0 => clock,

-- ERROR HERE

address_a => Mem_Addr,

--

q_a => Instruction
);
-- Instructions always start on a word address - not byte
PC(1 DOWNTO 0) <= "00";
-- copy output signals - allows read inside module
PC_out <= PC;
PC_plus_4_out <= PC_plus_4;
-- send word address to inst. memory address register
Mem_Addr <= Next_PC;
-- Adder to increment PC by 4
PC_plus_4( 9 DOWNTO 2 ) <= PC( 9 DOWNTO 2 ) + 1;
PC_plus_4( 1 DOWNTO 0 ) <= "00";
-- Mux to select Branch Address or PC + 4
Next_PC <= X"00" WHEN Reset = '1' ELSE
Add_result WHEN ( ( Branch = '1' ) AND ( Zero = '1' ) )
ELSE PC_plus_4( 9 DOWNTO 2 );
-- Store PC in register and load next PC on clock edge
PROCESS
BEGIN
WAIT UNTIL ( clock'EVENT ) AND ( clock = '1' );
IF reset = '1' THEN
PC <= "0000000000" ;
ELSE
PC( 9 DOWNTO 2 ) <= Next_PC;
END IF;
END PROCESS;
END behavior;

Answer 1

您要将ram的地址端口连接到一个名为mem_addr的信号-只有该信号不存在，因为您没有声明它。

您需要在其他信号旁边添加以下内容：

<script src="https://cdnjs.cloudflare.com/ajax/libs/jquery/3.3.0/jquery.min.js"></script>
<div id="wunderbiene">
        <img id="wunimg" src="https://upload.wikimedia.org/wikipedia/commons/9/91/Abeille-bee.svg" />
    </div>

Answer 2

首先，在实体声明中，不需要属性“ SIGNAL”。关于您的问题，您没有声明Mem_Addr信号。您必须在架构中声明它：

architecture BEHAVIOR of ...
begin
  signal Mem_Addr : std_logic_vector(X downto 0);

确保将X与您将其连接到的信号的长度1（address_a）匹配同样，您必须使用一些带有地址值的信号来驱动Mem_Addr信号。否则，该信号将具有不确定的值，或者等于默认值，并且不会影响数据存储器。

因此，要解决此问题，您必须确定实体中是否有任何信号携带您要传递到altsyncram内存的地址，或根据组件的输入信号确定如何确定它。

需要有关VHDL中的变量声明的帮助

2 个答案: