Question

在VHDL中，如何实现通过上拉驱动同一引脚的两个三态？我试图在Verilog中做同样的事情，它的合成没有任何问题：

`timescale 1ns/10ps

module driver(
    input  wire oe,
    input  wire di,
    output tri1 do
);
assign do = oe ? di : 1'bz;

endmodule

`timescale 1ns/10ps

module top(
    input  wire oe1,
    input  wire di1,
    input  wire oe2,
    input  wire di2,
    output tri1 do
);


driver driver1(
    .oe (oe1),
    .di (di1),
    .do (do)
);

driver driver2(
    .oe (oe2),
    .di (di2),
    .do (do)
);

endmodule

当我尝试用VHDL编写代码时，我有点卡住了，因为VHDL我不确定如何将Verilog的tri1“上拉”映射到VHDL。

library ieee;
use     ieee.std_logic_1164.all;

entity driver is
    port(
        oe :in  std_logic;
        di :in  std_logic;
        do :out std_logic
    );
end entity;

architecture rtl of driver is
begin
    do <= di when (oe = '1') else 'Z';
end architecture;

library ieee;
use     ieee.std_logic_1164.all;

entity top is
    port(
        oe1 :in std_logic;
        di1 :in std_logic;
        oe2 :in std_logic;
        di2 :in std_logic;
        do  :out std_logic
    );
end entity;

architecture rtl of top is
begin

    driver1: entity work.driver
        port map(
           oe => oe1,
           di => di1,
           do => do
        );

    driver2: entity work.driver
        port map(
           oe => oe2,
           di => di2,
           do => do
        );

    -- QUESTION: signal 'do' doesn't pull up to 'H' 
        ---when oe1='0' and oe2='0'..
    -- How to fix it in VHDL to do this so that pulls up
        -- like 'tri1' signal in the Verilog version of this code.
end architecture;

我尝试将驱动程序中的“ Z”更改为“ H” ...这导致合成失败，并警告多个驱动程序发出“ do”信号。

我尝试添加“ do <='H';”行。在VHDL上拉的另一个stackoverflow文章中建议将其转换为顶级架构。同样不起作用，综合失败，并警告多个驱动器发出“要做”的信号。

我的问题是：如何在VHDL代码中获得“ tri1”上拉功能，以在信号“ do”未驱动且两个驱动器都输出“ Z”时将信号“ do”上拉至“ H”。

Answer 1

如何在顶级架构中添加此行：

do <= 'Z' when (oe1 = '1') or (oe2 = '1') else 'H';

Answer 2

-- implementing a pullup...
-- this appears to synthesize in vivado without multiple driver error...

-------------------------------------
-- module: pullup
-------------------------------------
library ieee;
use     ieee.std_logic_1164.all;

-- pullup
entity pullup is
   port(
       di: in  std_logic;
       dz: out std_logic
   );
end entity; 

architecture rtl of pullup is
begin
    dz <= 'H' when (di = 'Z') else di;
end architecture;

-------------------------------------
-- module: driver
-------------------------------------
library ieee;
use     ieee.std_logic_1164.all;

entity driver is
    port(
        oe :in  std_logic;
        di :in  std_logic;
        do :out std_logic
    );
end entity;

architecture rtl of driver is
begin
    process(oe, di)
    begin
        if (oe = '1') then
            do <= di;
        else
            do <= 'Z';
        end if;
    end process;
end architecture;

-------------------------------------
-- module: top
-------------------------------------
library ieee;
use     ieee.std_logic_1164.all;

entity top is
    port(
        oe1 :in  std_logic;
        di1 :in  std_logic;
        oe2 :in  std_logic;
        di2 :in  std_logic;
        do  :out std_logic
    );
end entity;

architecture rtl of top is
   signal doz: std_logic;
begin

    driver1: entity work.driver
        port map(
           oe => oe1,
           di => di1,
           do => doz
        );

    driver2: entity work.driver
        port map(
           oe => oe2,
           di => di2,
           do => doz
        );

    pullup: entity work.pullup 
        port map(
           di => doz,
           dz => do
        );
    --do <= 'H' when (doz = 'Z') else doz;

end architecture;

在VHDL中，如何实现通过PULLUP驱动同一引脚的两个三态缓冲器？

2 个答案: