Question

我将信号filter_y_out和filter_x_out分开了，但我不知道如何使用它们

SIGNAL filter_y_out: STD_LOGIC_VECTOR(11 downto 0);
SIGNAL filter_x_out: STD_LOGIC_VECTOR(11 downto 0);
SIGNAL Final: STD_LOGIC_VECTOR(12 downto 0);
 -- SIGNAL Final_out: STD_LOGIC_VECTOR(12 downto 0);
SIGNAL filter_y_out_1: STD_LOGIC_VECTOR(7 downto 0);
SIGNAL filter_y_out_2: STD_LOGIC_VECTOR(7 downto 0);
SIGNAL filter_x_out_1: STD_LOGIC_VECTOR(7 downto 0);
SIGNAL filter_x_out_2: STD_LOGIC_VECTOR(7 downto 0);


COMPONENT Filter
Port ( clk : in STD_LOGIC;
       rst : in STD_LOGIC;
       valid_pixel_in : in STD_LOGIC;
       valid_pixel_out : out STD_LOGIC;
       en : in STD_LOGIC;
       pixel_in : in STD_LOGIC_VECTOR (7 downto 0);
       pixel_out : out STD_LOGIC_VECTOR (7 downto 0));
end COMPONENT;


COMPONENT Filter_x
Port ( clk : in STD_LOGIC;
       rst : in STD_LOGIC;
       valid_pixel_in : in STD_LOGIC;
       valid_pixel_out : out STD_LOGIC;
       en : in STD_LOGIC;
       pixel_in : in STD_LOGIC_VECTOR (7 downto 0);
       pixel_out : out STD_LOGIC_VECTOR (7 downto 0));
 end COMPONENT;


        Filter1: Filter --------------------------- y
        Port map(
               clk       => cam_pclk,
               rst       => reset,
               valid_pixel_in => fb_ena,
               valid_pixel_out => fb_ena_o,
               en        => filter_en,
               pixel_in  => cam_dat,
               pixel_out => filter_y_out
              -- pixel_out =>  filter_x_out_1  ---8b
               );




        Filter2: Filter_x  ---------------------------x
        Port map(
               clk       => cam_pclk,
               rst       => reset,
               valid_pixel_in => fb_ena,
               valid_pixel_out => fb_ena_o,
               en        => filter_en,
               pixel_in  => cam_dat,
               pixel_out => filter_x_out
              -- pixel_out => filter_x_out_2  ---8b
               );

  COMPONENT dsp48_add
      PORT (
        CLK : IN STD_LOGIC;
        A : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
        C : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
        P : OUT STD_LOGIC_VECTOR(12 DOWNTO 0)
      );
    END COMPONENT;  

   COMPONENT Final_sum
    PORT (
       CLK: IN STD_LOGIC;
       Final: OUT STD_LOGIC_VECTOR(12 downto 0)  --graysc is 8b
      );
 end COMPONENT;


      Final_adder : dsp48_add
      PORT MAP(
        CLK => cam_pclk,
        A => filter_x_out,    
        C => filter_y_out,    
        P => Final        ---12b
      );



    inst_Final: Final_sum
     Port map(
     CLK  => cam_pclk,
     Final => pixel_grayscale   ---8b
     );

[synth 8-549]端口'pixel_out'的端口宽度不匹配：端口宽度= 8，实际宽度= 12 [Synth 8-285]合成模块“ top”失败 [通用17-69]命令失败：综合失败-有关详细信息，请参见控制台或运行日志文件

Answer 1

首先，您的代码示例无法编译，组件声明和实例化仅按任何顺序抛出。

第二，组件pixel_out的端口Filter_x是std_logic_vector(7 downto 0)。在带有标签Filter2的实例中，端口映射将pixel_out连接到信号filter_x_out，该信号为std_logic_vector(11 downto 0)。如您所见，端口尺寸与连接的信号不匹配。错误消息中也提到了这一点。

如何在VHDL代码中使用零件选择中的分割零件？

1 个答案: