Question

我的代码中的某个点有一个8位输入，我想把这个输入分成2位。问题是我不能使用变量，我必须使用信号。如果我是一个整数，一切正常。如果我是一个信号，我怎么能这样做？

  signal part : std_logic_vector (1 downto 0);
  signal i    : std_logic_vector (2 downto 0);

begin

  part <= d_in(i downto i-1);

Answer 1

VHDL是一种强类型语言，因此需要integer类型作为索引 std_logic_vector，因此无法直接使用std_logic_vector。

您可以使用以下内容将i中的索引转换为整数 ieee.numeric_std库。见下面的例子：

library ieee;
use ieee.numeric_std.all;

architecture sim of tb is

  signal d_in : std_logic_vector(7 downto 0);
  signal part : std_logic_vector(1 downto 0);
  signal i    : std_logic_vector(2 downto 0);
  signal msb  : integer;  -- MSB index value

begin

  msb <= to_integer(unsigned(i));

  part <= d_in(msb downto msb - 1);

end architecture;

Answer 2

麻烦的是std_logic_vector只是一个没有内在含义的“包包”。它可能意味着一条指令，一段文字或一个有符号或无符号的数字。

正常的方法是使用numeric_std.unsigned代替std_logic_vector i，就像在signal i : unsigned (2 downto 0);中为这些位赋予意义一样。然后你可以写part <= d_in(to_integer(i) downto to_integer(i)-1)哪个有效，但很难看。整数类型的中间信号可能更清晰。

良好地使用VHDL涉及设计在进入这个混乱之前将使用的类型;它不会完全消除类型转换，但它会将它们降低到最小，例如在块之间的接口。

Answer 3

所有这些分析我运行了最后一个以确保没有运行时错误。

library ieee;
use ieee.std_logic_1164.all;

entity part_type_range is
end entity;

architecture fum of part_type_range is
    signal part:        std_logic_vector (1 downto 0);
    signal i:           std_logic_vector (2 downto 0);
    signal part1:       std_logic_vector (2 downto 1);
begin
    part  <= i(part1'range);
    part1 <= i(part1'range);
end architecture;

architecture fee of part_type_range is
    signal part:        std_logic_vector (1 downto 0);
    signal i:           std_logic_vector (2 downto 0);
    subtype partfield is  std_logic_vector (2 downto 1);
begin
    part <= i(partfield'range);
end architecture;

architecture twobitpieces of part_type_range is
    signal part1, part2, part3, part4:  std_logic_vector(1 downto 0);
    signal i:       std_logic_vector(7 downto 0);
    type union8 is array (1 to 4) of std_logic_vector(1 downto 0);
    signal part:    union8;
begin
    part <= union8'(i(7 downto 6),i(5 downto 4),i(3 downto 2),i(1 downto 0));
    -- part1 <= part(1);
    -- part2 <= part(2);
    -- part3 <= part(3);
    -- part4 <= part(4);  
       -- or in the alternative:
    (part1,part2,part3,part4) <= part;
       -- or use part(N) directly
end architecture;

architecture fie of part_type_range is


    signal part1, part2, part3, part4:  std_logic_vector(1 downto 0);
    signal i:       std_logic_vector(7 downto 0);
    type union8 is array (1 to 4) of std_logic_vector(1 downto 0);
    signal part:    union8;
    function to_union8 (a: std_logic_vector(7 downto 0)) return union8 is
        subtype part1 is std_logic_vector (7 downto 6);
        subtype part2 is std_logic_vector (5 downto 4);
        subtype part3 is std_logic_vector (3 downto 2);
        subtype part4 is std_logic_vector (1 downto 0);
    begin
        return union8'(a(part1'range),a(part2'range),a(part3'range),a(part4'range));
    end function;
begin
    part <= to_union8(i);
    -- part1 <= part(1);
    -- part2 <= part(2);
    -- part3 <= part(3);
    -- part4 <= part(4);  
       -- or in the alternative:
    (part1,part2,part3,part4) <= part;
       -- or use part(N) directly
end architecture;    

architecture foo of part_type_range is


    signal part1, part2, part3, part4:  std_logic_vector(1 downto 0);
    signal i:       std_logic_vector(7 downto 0);
    type union8 is array (1 to 4) of std_logic_vector(1 downto 0);
    function to_union8 (a: std_logic_vector(7 downto 0)) return union8 is
    begin
        return union8'(a(7 downto 6),a(5 downto 4),a(3 downto 2),a(1 downto 0));
    end function;
begin
    part1 <= to_union8(i)(1);
    part2 <= to_union8(i)(2);
    part3 <= to_union8(i)(3);
    part4 <= to_union8(i)(4);
end architecture;

在Brian的说法中，转换为4个两位值和输入8位值的并集赋予i意义而不使用无符号。

如何将信号分成几部分。 VHDL

3 个答案: