连接组件VHD。 RTL原理图无法正常工作

时间：2019-06-10 20:06:16

标签： entity vhdl

我已经建立了顶层实体，其中包含一些必须连接的其他组件。我一直在想问题出在哪里，但我不知道。没有问题，没有代码警告，只是我看不到clkdivider和vga（在rtl原理图中可以看到）以外的其他组件。有任何想法吗？我一直在尝试自己解决它，但是我没有其他任何想法为什么不起作用。在rtl示意图中，我可以看到vga组件通过clkdivider在TOP实体中连接，但是也应该与其他组件连接。

 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity TOP is
Port ( 


          TOP_reset : in std_logic;

       TOP_clk : in  STD_LOGIC;
          TOP_PS2D : in std_logic;
          TOP_PS2C : in std_logic;
       TOP_red : out  STD_LOGIC;
       TOP_green : out  STD_LOGIC;
       TOP_blue : out  STD_LOGIC;
          TOP_hs : out std_logic;
          TOP_vs : out std_logic
          );
end TOP;

architecture top_arch of TOP is
component keycontroller
         port(
           clk25 : in std_logic;
            clr : in std_logic;
            PS2C : in std_logic;
            PS2D : in std_logic;
            keyval1 : out std_logic_vector(7 downto 0);
            keyval2 : out std_logic_vector(7 downto 0);
            keyval3 : out std_logic_vector(7 downto 0)
            );
end component keycontroller;
component Display_acc
         port( 
            keyval_in1 : in std_logic_vector(7 downto 0);
            keyval_in2 : in std_logic_vector(7 downto 0);
            keyval_in3 : in std_logic_vector(7 downto 0);

          ZNAK_Z_ROM : in std_logic_vector(47 downto 0):=(others=>'0');
       vs : out  STD_LOGIC_VECTOR (9 downto 0):=(others=>'0');
       hs : out  STD_LOGIC_VECTOR (9 downto 0):=(others=>'0');
       adresROM : out  STD_LOGIC_VECTOR (4 downto 0);
          clk : in std_logic);
 end component Display_acc;     

 component VGA
 port(
    clk : in std_logic;
    hs_character : in std_logic_vector(9 downto 0);
    vs_character : in std_logic_vector(9 downto 0);
    reset : in std_logic;
    vs_out : out std_logic;
    hs_out : out std_logic;
    red : out std_logic;
    green: out std_logic;
    blue : out std_logic);
  end component VGA;


   component clkdivider
   port(
          clk   : in  STD_LOGIC;    -- sygnal zegarowy z FPGA 50MHz (C9)
        reset   : in  STD_LOGIC;    -- reset asynchroniczny

          -- WYJSCIA --
          clk25     : out STD_LOGIC -- wyjscie z sygnalem zegarowym o okreslonej czestotliwosci, tutaj 25MHz


        );
end component;

component ROM
Port (
        adresROM : in  STD_LOGIC_VECTOR (4 downto 0);
     daneROM : out  STD_LOGIC_VECTOR (47 downto 0));
 end component;
 signal address_character_rom : std_logic_vector(4 downto 0);
 signal data_character_rom : std_logic_vector(47 downto 0);
 signal vertical_synch : std_logic_vector(9 downto 0);
 signal horizontal_synch : std_logic_vector(9 downto 0);
 signal hs_output : std_logic;
 signal vs_output : std_logic;
 signal clkps2: std_logic;
 signal keyval_out1 : std_logic_vector(7 downto 0);
 signal keyval_out2 : std_logic_vector(7 downto 0);
 signal keyval_out3 : std_logic_vector(7 downto 0);
 --wejsice tego co odbiera trzeba skierowac na sygnal wew
 begin
 blok1 : keycontroller port map(
 clr=>TOP_reset,
 PS2C => TOP_PS2C,
 PS2D => TOP_PS2D,                                  
 keyval1 => keyval_out1,
 keyval2 => keyval_out2,
 keyval3 => keyval_out3,
 clk25 => clkps2


                                    );
---------------------------------                                       
blok2 : display_acc port map(
clk => clkps2,
keyval_in1 =>keyval_out1,
keyval_in2 =>keyval_out2,
keyval_in3 =>keyval_out3,
ZNAK_Z_ROM =>data_character_rom,
vs => vertical_synch,
hs => horizontal_synch,
adresROM =>address_character_rom
);
-------------------------------
blok3: clkdivider port map
( clk=>TOP_clk,
reset=>TOP_reset,
clk25 => clkps2

);
----------
blok4 : VGA port map
(
clk=>clkps2,--25mhz
hs_character =>horizontal_synch,
vs_character => vertical_synch,
reset=>TOP_reset,
vs_out =>TOP_vs,
hs_out => TOP_hs,
green => TOP_green,
red => TOP_red,
blue => TOP_blue
);
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity TOP is
Port ( 


          TOP_reset : in std_logic;

       TOP_clk : in  STD_LOGIC;
          TOP_PS2D : in std_logic;
          TOP_PS2C : in std_logic;
       TOP_red : out  STD_LOGIC;
       TOP_green : out  STD_LOGIC;
       TOP_blue : out  STD_LOGIC;
          TOP_hs : out std_logic;
          TOP_vs : out std_logic
          );
end TOP;

architecture top_arch of TOP is
component keycontroller
         port(
           clk25 : in std_logic;
            clr : in std_logic;
            PS2C : in std_logic;
            PS2D : in std_logic;
            keyval1 : out std_logic_vector(7 downto 0);
            keyval2 : out std_logic_vector(7 downto 0);
            keyval3 : out std_logic_vector(7 downto 0)
            );
end component keycontroller;
component Display_acc
         port( 
            keyval_in1 : in std_logic_vector(7 downto 0);
            keyval_in2 : in std_logic_vector(7 downto 0);
            keyval_in3 : in std_logic_vector(7 downto 0);

          ZNAK_Z_ROM : in std_logic_vector(47 downto 0):=(others=>'0');
       vs : out  STD_LOGIC_VECTOR (9 downto 0):=(others=>'0');
       hs : out  STD_LOGIC_VECTOR (9 downto 0):=(others=>'0');
       adresROM : out  STD_LOGIC_VECTOR (4 downto 0);
          clk : in std_logic);
 end component Display_acc;     

 component VGA
 port(
    clk : in std_logic;
    hs_character : in std_logic_vector(9 downto 0);
    vs_character : in std_logic_vector(9 downto 0);
    reset : in std_logic;
    vs_out : out std_logic;
    hs_out : out std_logic;
    red : out std_logic;
    green: out std_logic;
    blue : out std_logic);
  end component VGA;


   component clkdivider --divide frequency of board
   port(
          clk   : in  STD_LOGIC;    -- sygnal zegarowy z FPGA 50MHz (C9)
        reset   : in  STD_LOGIC;    -- reset asynchroniczny

          -- WYJSCIA --
          clk25     : out STD_LOGIC -- wyjscie z sygnalem zegarowym o okreslonej czestotliwosci, tutaj 25MHz


        );
end component;

component ROM
Port (
        adresROM : in  STD_LOGIC_VECTOR (4 downto 0);
     daneROM : out  STD_LOGIC_VECTOR (47 downto 0));
 end component;
 --signals which are used to send data
 signal address_character_rom : std_logic_vector(4 downto 0);
 signal data_character_rom : std_logic_vector(47 downto 0);
 signal vertical_synch : std_logic_vector(9 downto 0);
 signal horizontal_synch : std_logic_vector(9 downto 0);
 signal hs_output : std_logic;
 signal vs_output : std_logic;
 signal clkps2: std_logic;
 signal keyval_out1 : std_logic_vector(7 downto 0);
 signal keyval_out2 : std_logic_vector(7 downto 0);
 signal keyval_out3 : std_logic_vector(7 downto 0);
 --wejsice tego co odbiera trzeba skierowac na sygnal wew
 begin
 blok1 : keycontroller port map(
 clr=>TOP_reset,
 PS2C => TOP_PS2C,
 PS2D => TOP_PS2D,                                  
 keyval1 => keyval_out1,
 keyval2 => keyval_out2,
 keyval3 => keyval_out3,
 clk25 => clkps2


                                    );
---------------------------------                                       
blok2 : display_acc port map(
clk => clkps2,
keyval_in1 =>keyval_out1,
keyval_in2 =>keyval_out2,
keyval_in3 =>keyval_out3,
ZNAK_Z_ROM =>data_character_rom,
vs => vertical_synch,
hs => horizontal_synch,
adresROM =>address_character_rom
);
-------------------------------
blok3: clkdivider port map
( clk=>TOP_clk,
reset=>TOP_reset,
clk25 => clkps2

);
----------
blok4 : VGA port map
(
clk=>clkps2,--25mhz
hs_character =>horizontal_synch,
vs_character => vertical_synch,
reset=>TOP_reset,
vs_out =>TOP_vs,
hs_out => TOP_hs,
green => TOP_green,
red => TOP_red,
blue => TOP_blue
);
blok5 : ROM port map 
(
adresROM => address_character_rom,
daneROM => data_character_rom

);

end top_arch;

1 个答案:

答案 0 :(得分：0)

如果RTL原理图是在合成后生成的：

综合工具进行了大量优化，删除了无用的代码部分。它还可以包含另一个实例中的一些代码部分。

这取决于您的综合工具参数，但通常它会删除设计中的所有层次结构（组件）以合成“平面设计”，然后为用户重建层次结构，但组件的边界可能位于不同的位置或组件可以在合成后的RTL原理图中删除。

如果您没有看到某些组件，则并不意味着它们的功能不在此处。功能可以包含在其他组件（ VGA ）中。

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