在启动原理图时显示错误，并且未显示rtl原理图

Question

我的代码

library ieee;
use ieee.std_logic_1164.all;

entity LG is
port (A, B: in BIT; C: out BIT);
end;

architecture LG1 of LG is
begin
C<=A and B;
end;

显示以下错误：

# Debug data file, vsim.dbg, does not exist.
# 
# Invoke vsim with -debugDB to create this file.
# Debug data file, vsim.dbg, does not exist.
# 
# Invoke vsim with -debugDB to create this file.
# Could not open the database because the required debug information has not been generated.
# Please refer to the documentation for additional details.