Question

我在Verilog中具有以下模块，用于在电线上施加延迟：

  module DelayModule (input_signal, delayed_signal);
    output  delayed_signal;
    input input_signal;
    wire [16:1] dummy_wire;
    wire [16:1] other = {dummy_wire[15:1],input_signal};
    assign delayed_signal =  dummy_wire[16];
    BUFX12 BUF [16:1] (.A(other),.Y(dummy_wire));
  endmodule

我希望使该模块能够使用输入参数使该模块的延迟根据输入参数变化。像这样：

module DelayModule (input_signal, delayed_signal,k);
    output  delayed_signal;
    input input_signal;
    integer k;
    wire [k:1] dummy_wire;
    wire [k:1] other = {dummy_wire[k-1:1],input_signal};
    assign delayed_signal =  dummy_wire[k];
    BUFX12 BUF [k:1] (.A(other),.Y(dummy_wire));
endmodule

此声明在Verilog中是不允许的，但我正在寻找一种技术来实现这样的事情：模块接受诸如k之类的某些参数，但是模块内部的缓冲区数和连接线是此{{1 }}值。我想知道是否可以做这样的事情，或者做点什么在Verilog中实现这个想法？

Answer 1

仅允许通过Verilog参数（通常实现为传递到实例化位置的目标模块的层次结构参数）来允许此操作。请注意，这将是编译时选项，因此您将无法在控制器运行期间对其进行更改。下面是解释此概念的代码段：

//----------------------------------------------------
// Module Name: dff_sync.v
//----------------------------------------------------
// Description: conventional 2xFF sync module with parameterizable options
//              such as:
//              - (1) Reset Value - DFF_SYNC_RESET_VALUE
//              - (2) Number of FF stages - DFF_SYNC_NUM_FF_STAGES
//              - (3) Input Bus width - DFF_SYNC_INP_BUS_WIDTH
//
// TBD:
//     - application of random delay (+/- 1 clk cycle), as it is the best evidence
//       of bug-free CDC functinal implementation.
//----------------------------------------------------

module dff_sync #
(
    parameter DFF_SYNC_RESET_VALUE   = 'b0,
    parameter DFF_SYNC_NUM_FF_STAGES = 'd2,
    parameter DFF_SYNC_INP_BUS_WIDTH = 'd1
)
(
    input                               clk,
    input                               rst_n,
    input  [DFF_SYNC_INP_BUS_WIDTH-1:0] data_in,
    output [DFF_SYNC_INP_BUS_WIDTH-1:0] data_out
);

    /* packed dimension */                 /* unpacked dimension*/
reg [DFF_SYNC_NUM_FF_STAGES-1:0] dff_chain [DFF_SYNC_INP_BUS_WIDTH-1:0];

// Note: multi-dimensional array can be accessed as shown below
//       reg [7:0] regA [3:0]
//       regA[unpacked_3_thru_0][packed_7_thru_0]

    genvar i;
    generate
        // iterate through unpacked dimension...
        for (i = 0; i < DFF_SYNC_INP_BUS_WIDTH; i = i + 1)
        begin: g_dff_sync

            always @(posedge clk or negedge rst_n)
            begin: p_sync_chain
                if (!rst_n)
                    dff_chain[i] <= {DFF_SYNC_NUM_FF_STAGES{DFF_SYNC_RESET_VALUE}};
                else
                    dff_chain[i] <= {dff_chain[i][DFF_SYNC_NUM_FF_STAGES-1:1],data_in[i]};
            end // p_sync_chain

            assign data_out[i] = dff_chain[i][DFF_SYNC_NUM_FF_STAGES-1];

        end // g_dff_sync
    endgenerate

endmodule // dff_sync

以及下面的代码，您可以实例化此模块的变体，从而产生具有RESET_VALUE = 0，NUM_FF_STAGES = 2和INP_BUS_WIDTH = 1的2xFF同步器：

 dff_sync #
    (
        .DFF_SYNC_RESET_VALUE ('d0),
        .DFF_SYNC_NUM_FF_STAGES ('d2),
        .DFF_SYNC_INP_BUS_WIDTH ('d1)
    )
    i_dff_sync
    (
        // ---- Inputs ----
        .clk      (clk),
        .rst_n    (rst_n),
        .data_in  (data_in),

        // ---- Outputs ----
        .data_out (data_out)
    ); // i_dff_sync

如何在Verilog中定义参数模块？

1 个答案: