Question

我试图用https://forums.xilinx.com/t5/Embedded-Development-Tools/bidirectional-tristate-in-out-port-in-Vivado/td-p/352239来理解verilog，特别是inout port。

我已按照以下方式实施了解。但是我觉得使用“my_top”＆＃39; tb模块中的模块

如何连接到＆＃39; my_top＆＃39;模块在＆＃39; tb＆＃39;模块？我也希望使用初始语句在tb模块中测试my_top模块。

如何连接以查看tb模块中my_top模块的工作情况？

module tb;

reg     data_tri;
reg     data_tx;
reg     data_rx;
wire    data_io;


my_top u_my_top(
  .data_tri (   data_tri            ),
  .data_tx  (   data_tx         ),
  .data_rx  (   data_rx         ),
  .data_io  (   data_io         )
  );

initial begin
#30 
//inout write 
data_tri = 0; 
data_tx = 1; 
//inout read 
data_tri = 1; 
data_io = 1;
end

endmodule


module my_top (
  input  data_tri,
  input  data_tx,
  output data_rx,
  inout  data_io
  );

assign data_io = (data_tri) ? 1'bZ : data_tx;
assign data_rx = data_io;

endmodule

Answer 1

您需要在测试平台中以与设计中完全相同的方式驱动三态信号（使用电线）：

assign data_io = (data_tri) ? data_txtb : 1'bZ;

所以，例如：

module tb;

reg     data_tri;
reg     data_tx;
reg     data_txtb;
wire    data_rx;
wire    data_io;

  my_top u_my_top(
    .data_tri (   data_tri        ),
    .data_tx  (   data_tx         ),
    .data_rx  (   data_rx         ),
    .data_io  (   data_io         )
  );

  assign data_io = (data_tri) ? data_txtb : 1'bZ;

  initial begin
    $dumpfile("dump.vcd"); $dumpvars;

    //inout write 
    data_tri = 0; 
    data_tx = 1; 
    #30 
    data_tx = 0; 
    #30 
    data_tx = 1; 

    #30 
    //inout read 
    data_tri = 1; 
    data_txtb = 0; 
    #30 
    data_txtb = 1; 
    #30 
    data_txtb = 0; 
    #30; 
  end

endmodule

https://www.edaplayground.com/x/342E

如何连接其他模块中其他模块的inout端口？

1 个答案: