VHDL代码,用于在七段显示器上驱动8位数字

时间:2019-05-15 21:03:26

标签: vhdl

我已经为4位七段显示器编写了代码,并且我试图对其进行修改以驱动nexys 4 ddr的七段显示器上的所有8位数字。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity eAfisareDistanta is
 Port (
       digit0: in std_logic_vector(7 downto 0);
       digit1: in std_logic_vector(7 downto 0);
       digit2: in std_logic_vector(7 downto 0);
       digit3: in std_logic_vector(7 downto 0);
       digit4: in std_logic_vector(7 downto 0);
       digit5: in std_logic_vector(7 downto 0);
       digit6: in std_logic_vector(7 downto 0);
       digit7: in std_logic_vector(7 downto 0);  
       clk: in std_logic;
       cat: out std_logic_vector(6 downto 0);
       an: out std_logic_vector(7 downto 0));
 end eAfisareDistanta;

architecture aAfisareDistanta of eAfisareDistanta is

signal i0: std_logic_vector(7 downto 0):="1110";
signal i1: std_logic_vector(7 downto 0):="1101";
signal i2: std_logic_vector(7 downto 0):="1011";
signal i3: std_logic_vector(7 downto 0):="0111";
signal i4: std_logic_vector(7 downto 0):="0111";
signal i5: std_logic_vector(7 downto 0):="0111";
signal i6: std_logic_vector(7 downto 0):="0111";
signal i7: std_logic_vector(7 downto 0):="0111";
signal count: std_logic_vector(15 downto 0):=x"0000";
signal m1: std_logic_vector(7 downto 0);

begin

process(clk)
      begin
      if rising_edge(clk) then
        count <= count +1;
      end if;
end process;

process(digit0, digit1, digit2, digit3, count(15 downto 14))
    begin 
    case count(15 downto 14) is
        when "00" => m1 <= digit0;
        when "01" => m1 <= digit1;
        when "10" => m1 <= digit2;
        when others => m1<=digit3;
    end case;

end process;

process(i0, i1,i2,i3, count(15 downto 14))
   begin 
    case count(15 downto 14) is 
        when "00" => an<=i0; 
        when "01" => an<=i1;
        when "10" => an<=i2;
        when others => an<=i3;
     end case;
 end process;

 process(m1)
 begin 
  case m1 is
          when "0000" => cat <= "1000000";   --0
          when "0001" => cat <= "1111001";   --1
          when "0010" => cat <= "0100100";   --2
          when "0011" => cat <= "0110000";   --3
          when "0100" => cat <= "0011001";   --4
          when "0101" => cat <= "0010010";   --5
          when "0110" => cat <= "0000010";   --6
          when "0111" => cat <= "1111000";   --7
          when "1000" => cat <= "0000000";   --8
          when "1001" => cat <= "0010000";   --9
          when "1010" => cat <= "0001000";   --A
          when "1011" => cat <= "0000011";   --b
          when "1100" => cat <= "1000110";   --C
          when "1101" => cat <= "0100001";   --d
          when "1110" => cat <= "0000110";   --E
          when others => cat <= "0001110";   --F
     end case;
  end process;

end aAfisareDistanta;

是的。我想我必须将多路复用器修改为8比1或什么? 我知道nexys 4的阴极很常见,但是我不太清楚显示器的工作原理。

0 个答案:

没有答案