Question

我需要设计一组四个4位寄存器，其内容显示在七段显示器上。因此，基本上只需在7段上显示4个十六进制数字。输出在每个时钟周期自行切换。我正在使用Basys2板。这就是我到目前为止......

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Register_Bank is
port( x: in std_logic_vector(3 downto 0);
        disp_en: out std_logic_vector(3 downto 0);
        z:  out std_logic_vector(7 downto 0);
        ck,reset: in std_logic);
end Register_Bank;

architecture Behavioral of Register_Bank is

Type my_state is(s0,s1,s2,s3);
Signal n_s: my_state;
Signal ck_div: std_logic;
Signal temp,temp1,temp2,temp3,temp0,temp_main: std_logic_vector(0 to 3);
Signal R0,R1,R2,R3 : std_logic_vector(3 downto 0);

begin

-- 
process(temp_main)
begin
case temp_main is
    when "0000" => z <= "00000011";
    when "0001" => z <= "10011111";
    when "0010" => z <= "00100101";
    when "0011" => z <= "00001101";
    when "0100" => z <= "10011001";
    when "0101" => z <= "01001001";
    when "0110" => z <= "01000001";
    when "0111" => z <= "00011111";
    when "1000" => z <= "00000001";
    when "1001" => z <= "00001001";
    when "1010" => z <= "00010001";
    when "1011" => z <= "11000001";
    when "1100" => z <= "01100011";
    when "1101" => z <= "10000101";
    when "1110" => z <= "01100001";
    when "1111" => z <= "01110001";
    when others => null;

--temp3 <= x<3>;
--temp2 <= x<2>;
--temp1 <= x<1>;
--temp0 <= x<0>;

--wiring the register contents to outputs
temp3 <= R3;
temp2 <= R2;
temp1 <= R1;
temp0 <= R0;

--state machine for TMD
Process(x,ck_div)
begin
if ck_div ='1' and ck_div'event then
case n_s is
    when s0 => 
        temp <= x<0>; 
        disp_en <= "0111";
        n_s <= s1;
    when s1 =>
        temp <= x<1>;
        disp_en <= "1011";
        n_s <= s2;
    when s2 =>
        temp <= x<2>;
        disp_en <= "1101";
        n_s <= s3;
    when s3 =>
        temp <= x<3>;
        disp_en <= "1110";
        n_s <= s0;  
end case;
end if;
end process;

-- clock division
process(ck)
variable count: integer;
begin
if ck ='1' and ck'event then
    if reset ='1' then
        count := 0;
        ck_div <= '0';
    elsif reset ='0' then
        if count = 999999 then
            ck_div <= not ck_div;
            count := 0;
        else
            count := count + 1;
        end if; 
    end if;
end if;
end process;    

end Behavioral;

我知道逻辑已关闭，并且还存在语法错误。我需要帮助尝试调试这个。我非常感谢帮助！

Answer 1

首先，请勿使用ck_div作为时钟。更改代码，使其在1000000中的一个刻度变高。然后更改主进程以将该信号用作启用：

if rising_edge(clk) and ck_div = '1' then

这使您的设计与一个时钟完全同步，这意味着工具可以更轻松地找到生活 - 而且您可以做的任何事情都可以让工具更轻松，这对设计师来说是一个胜利。

Answer 2

如果您尝试提交至少在语法上正确的代码，那就太好了。如果您运行ModelSim（或通过Sigasi编辑器），您将看到两个微不足道的语法错误：

缺少两个“END”关键字
矢量切片使用圆括号：x(1)，而非菱形x<1>

只有在修复此问题后，您才能处理设计的行为。

您可能需要在此处查看一些代码：http://www.sigasi.com/content/7-segment-display

七段的十六进制数

2 个答案: