七段显示的Verilog代码错误

时间:2018-11-06 16:47:50

标签: verilog

我已尝试将此代码的每个变体用于七段显示代码,并且始终显示错误。我不知道为什么。

  File "/src/first.py", line 91, in deliver_table
    call = second.main(sys.argv[1:])
  File "/src/second.py", line 427, in main
    args = _parse_args(argv)
  File "/src/second.py", line 51, in _parse_args
    return parser.parse_args(args)
  File "/app/python/2.7.5/LMWP3/lib/python2.7/argparse.py", line 1688, in parse_args
    args, argv = self.parse_known_args(args, namespace)
  File "/app/python/2.7.5/LMWP3/lib/python2.7/argparse.py", line 1720, in parse_known_args
    namespace, args = self._parse_known_args(args, namespace)
  File "/app/python/2.7.5/LMWP3/lib/python2.7/argparse.py", line 1944, in _parse_known_args
    self.error(_('argument %s is required') % name)
  File "/app/python/2.7.5/LMWP3/lib/python2.7/argparse.py", line 2361, in error
    self.exit(2, _('%s: error: %s\n') % (self.prog, message))
  File "/app/python/2.7.5/LMWP3/lib/python2.7/argparse.py", line 2349, in exit
  _ sys.exit(status)
SystemExit: 2

2 个答案:

答案 0 :(得分:1)

如果您仅解释“说错误”,它将帮助其他人更快地理解您的问题。我假设您遇到语法错误,因为您使用的是单引号'

答案 1 :(得分:1)

您可能在编辑器中使用utf-8编码。这可能会导致无法打印的Unicode字符。如果可以,请切换到ascii-8。这是编译的固定代码:

module sevensegment (input [3:0] bcd, output reg [6:0] seg);
always @ (*)
      case(bcd)
      0: seg = 7'b0111111; 
      1: seg = 7'b0000110;   
      2: seg = 7'b1011011;
      3: seg = 7'b1001111;
      4: seg = 7'b1100110;
      5: seg = 7'b1101101;
      6: seg = 7'b1111101;
      7: seg = 7'b0000111;
      8: seg = 7'b1111111;
      9: seg = 7'b1101111;
      default:  seg = 7'b0000000;
    endcase  
endmodule