使用Verilog进行七段显示

时间:2014-04-24 11:42:34

标签: verilog

大家好!

我正在做我最后的项目,我发现自己迷路了。基本上我要做的是使用我的Basys板作为8位有符号数字转换器。所以有八个开关作为输入来输入一个带符号的数字,例如10111110.然后我想取这个数字并通过2的恭维把它转换成它的等效十进制值。然后我想在七段显示器上显示数字。我会喜欢有关如何开始的任何提示或建议,因为我无法弄清楚我如何获取数字并在显示器上显示它。我会发布我的代码,期待阅读你们给我的任何建议。谢谢你的帮助!

input load, cup, cdown, rst;
input Sw7, Sw6, Sw5, Sw4, Sw3, Sw2, Sw1, Sw0;
output MyNumber[7];

seg7 h1(w, x, y, z, a, b, c, d, e,f,g);
clockdivider h2(clk0, ClkOut);


initial begin
MyNumber <= 8'b0000000;

end

always @(MyNumber)
w <= MyNumber[7]
MyNumber[6]
MyNumber[5]
MyNumber[4]
MyNumber[3]
MyNumber[2]
MyNumber[1]
MyNumber[0]
end

always @(posedge clk) begin

if(rst) begin
    MyNumber <=0;

end else if (cup) begin
    MyNumber = MyNumber + 1;

end else if (cdown) begin
    MyNumber = MyNumber - 1;

end else if (load) begin
    MyNumber[7] <= Sw0;
    MyNumber[6] <= Sw1;
    MyNumber[5] <= Sw2;
    MyNumber[4] <= Sw3;
    MyNumber[3] <= Sw4;
    MyNumber[2] <= Sw5;
    MyNumber[1] <= Sw6;
    MyNumber[0] <= Sw7;

end


end

这是我的七段显示代码

input w, x, y, z;
output reg a, b, c, d, e,f,g;
reg [6:0] a_to_g;
reg [3:0] w_to_z;

initial begin
w_to_z[3] = w;
w_to_z[2] = x;
w_to_z[1] = y;
w_to_z[0] = z;
a=0;b=0;c=0;d=0;e=0;f=0;g=0;
end 

always @(*) begin
    w_to_z[3] = w;
w_to_z[2] = x;
w_to_z[1] = y;
w_to_z[0] = z;
case(w_to_z)
    0:a_to_g=7'b0000001;
    1:a_to_g=7'b1001111;
    2:a_to_g=7'b0010010;
    3:a_to_g=7'b0000110;
   4:a_to_g=7'b1001100;
    5:a_to_g=7'b0100100;
    6:a_to_g=7'b0100000;
    7:a_to_g=7'b0001111;
    8:a_to_g=7'b0000000;
    9:a_to_g=7'b0000100;
    'ha:a_to_g=7'b0001000;
    'hb:a_to_g=7'b1100000;
    'hc:a_to_g=7'b0110001;
    'hd:a_to_g=7'b1000010;
    'hf:a_to_g=7'b0111000;
    default a_to_g=7'b1111111;
endcase
a = a_to_g[6];
b = a_to_g[5];
c = a_to_g[4];
d = a_to_g[3];
e = a_to_g[2];
f = a_to_g[1];
g = a_to_g[0];
end

而且我完全不想离开,因为我正在寻找有人为我做任务。我只是输了,可以用正确的方向推进,谢谢大家。

0 个答案:

没有答案