Quartus II VHDL代码问题-我该怎么办？

Question

我正在尝试在Quartus II中编译我的VHDL代码，但由于显然存在一（1）错误而无法编译。问题是，程序没有显示错误在哪里或错误是什么。我已经待了好几天了。有人可以帮忙吗？

顺便说一句，我知道代码是针对VHDL软件包的，主要代码是可以的，只是Quartus II向我抛出未知错误，我不知道该怎么办。我已经尝试了所有方法-添加内容，删除内容，但是仍然抛出“ [文件名]不成功（1个错误）”。

library ieee;
use ieee.std_logic_1164.all;
package package1 is
    component NOT1
        generic(DELAY: time:=5ns);
        port(in1,in2: in std_logic; out1: out std_logic);
    end component;

    component AND2
        generic(DELAY: time:=5ns);
        port(in1,in2: in std_logic;out1: out std_logic);
    end component;

    component OR2
        generic(DELAY: time:=5ns);
        port(in1,in2: in std_logic;out1: out std_logic);
    end component;

    component XOR2
        generic(DELAY: time:=5ns);
        port(in1,in2: in std_logic;out1: out std_logic);
    end component;

    component ADD3
        generic(DELAY:time:=5ns);
        port(in1,in2,cin: in std_logic;sum,cout:out std_logic);
    end component;

    component INVERT3
        generic(delay:time:=5ns);
        port(in1,in2,in3:in std_logic; out1:out std_logic);
    end component;

    component OPERATION5
        generic(delay:time:=5ns);
        port(in1,in2,in3,in4,in5:in std_logic;out1:out std_logic);
    end component;
end package package1;

library ieee;
use ieee.std_logic_1164.all;
package body package1 is

    entity AND2 is
        generic(delay:time);
        port(in1,in2:in std_logic;out1:out std_logic);
    end AND2;
    architecture model_conc of AND2 is
        begin
            out1 <= in1 and in2 after delay;
    end model_conc;

    entity NOT1 is
        generic(delay:time);
        port(in1:in std_logic;out1:out std_logic);
    end NOT1;
    architecture model_conc1 of NOT1 is
        begin
            out1 <= not in1 after delay;
    end model_conc1;

    entity OR2 is
        generic(delay:time);
        port(in1,in2:in std_logic;out1:out std_logic);
    end OR2;
    architecture model_conc2 of OR2 is
        begin
            out1 <= in1 or in2 after delay;
    end model_conc2;

    entity XOR2 is
        generic(delay:time);
        port(in1,in2:in std_logic;out1:out std_logic);
    end XOR2;
    architecture model_conc3 of XOR2 is
        begin
            out1 <= in1 xor in2 after delay;
    end model_conc3;

    entity ADD3 is
        generic(delay: time);
        port(in1,in2,cin: in std_logic;sum,cout:out std_logic);
    end ADD3;
    architecture model_conc4 of ADD3 is
        begin   
            sum <= (in1 AND NOT in2 AND NOT cin) OR (NOT in1 AND in2 AND NOT cin) OR (NOT in1 AND NOT in2 AND cin) OR (in1 AND in2 AND cin);
            cout <= (in2 AND cin) OR (in1 AND cin) OR (in1 AND in2);
    end model_conc4;

    entity INVERT3 is
        generic(delay:time);
        port(in1,in2,in3:in std_logic; out1:out std_logic);
    end INVERT3;
    architecture model_conc5 of INVERT3 is
        begin
            if (in3=1) then
                out1 <= in1;
            else 
                out1 <= in2;
            end if; 
            after delay;
    end model_conc5;

    entity OPERATION5 is
        generic(delay:time);
        port(in1,in2,in3,in4,in5:in std_logic;out1:out std_logic);
    end OPERATION5;
    architecture model_conc6 of OPERATION5 is
        begin
            if in5=0 then
                out1 <= in1;
            elsif in5=1 then
                out1 <= in2;
            elsif in5=2 then
                out1 <= in3;
            else 
                out1<=in4;
            end if; 
            after delay;
    end model_conc6;




end package body package1;