如何解决VHDL中的代码错误?

时间:2019-04-23 14:40:59

标签: syntax-error vhdl quartus

我编写了执行算术和逻辑运算的代码。但是,当我进行编译时,报告显示我有很多语法错误。我是VHDL的初学者,我真的不知道如何纠正这些错误,你能给我一些建议吗?

1  library ieee;
2  use ieee.std_logic_1164.all;
3  use ieee.std_logic_unsigned.all;
4  use ieee.numeric_std.all;
5
6  package arith_operations is
7   constant size: integer :=8;
8   constant select_bits: integer :=3;
9   procedure add( x,y: in bit_vector(size-1 downto 0);
10                 sum: out bit_vector(size-1 downto 0); c_out: out bit );
11  procedure sub( x,y: in bit_vector(size-1 downto 0);
12                   d: out bit_vector(size-1 downto 0); c_out: out bit );
13  function inc(x: in bit_vector) return bit_vector;
14  function dec(x: in bit_vector) return bit_vector;
15  end arith_operations;
16
17 package body arith_operations is
18  procedure add( x,y: in bit_vector(size-1 downto 0); sum: out bit_vector(size-1 downto 0);
19               c_out: out bit);
20  variable s: bit_vector(size downto 0);
21  begin
22   s:= "0" & x + "0" & y;
23   sum:= s(size-1 downto 0);
24   c_out:= s(size);
25  end add; 
26  procedure sub( x,y: in bit_vector(size-1 downto 0);sum: out bit_vector(size-1 downto 0;
27                c_out: out bit);
28  variable s: bit_vector(size downto 0);
29  begin 
30    s:= "0" x + not("0"& y) + ((size-1 downto 0)=>"0") & "1";
31    d:= s(size-1 downto 0);
32    c_out:= s(size);
33  end sub;
34  function inc(x: in bit_vector(size-1 downto 0)) return bit_vector is
35  variable x1: bit_vector(size-1 downto 0);
36  begin
37    x1:= x + ((size-2 downto 0)=>"0") & "1";
38    return x1;
39  end inc;
40 
41  function dec(x: in bit_vector(size-1 downto 0)) return bit_vector is
42  variable x1: bit_vector(size-1 downto 0);
43  begin
44    x1:= x + ((size-1 downto 0)=> "1"); 
45    return x1;
46  end dec;
47 end arith_operations;
48
49 use work.arith_operations.all;
50
51 entity alu is
52 generic(delay :time);
53 port( x,y: in bit_vector(size-1 downto 0);
54       function_select: in bit_vector(size-1 downto 0);
55      f: out bit_vector(size-1 downto 0);
56 end alu;
57
58 architecture behave of alu is:
59 begin
60   p0: process(x,y,function_select) 
61   variable f_out: bit_vector(size-1 downto 0);
62   begin
63     case function_select is
64      when "000" => add (x, y, f_out); f<= f_out after delay;
65      when "001" => sub(x, y, f_out); f<= f_out after delay; 
66      when "010" => f <= inc(x) after delay; 
67      when "010" => f <= dec(x) after delay; 
68      when "100" => x or y after delay; 
69      when "101" => not x after delay; 
70      when "110" => x and y after delay; 
71      when "111" => x xor y after delay; 
72     end case function_select;
73   end process p0;
74 end architecture behave;

这也是错误:

Error (10500): VHDL syntax error at Alu.vhd(21) near text "begin";  expecting "end", or a declaration statement
Error (10396): VHDL syntax error at Alu.vhd(25): name used in construct must match previously specified name "arith_operations"
Error (10500): VHDL syntax error at Alu.vhd(26) near text "procedure";  expecting "entity", or "architecture", or "use", or "library", or "package", or "configuration"
Error (10500): VHDL syntax error at Alu.vhd(56) near text "end";  expecting an identifier ("end" is a reserved keyword), or "constant", or "file", or "signal", or "variable"
Error (10500): VHDL syntax error at Alu.vhd(60) near text ")";  expecting ":", or ","
Error (10500): VHDL syntax error at Alu.vhd(62) near text "begin";  expecting an identifier ("begin" is a reserved keyword), or "constant", or "file", or "signal", or "variable"
Error (10500): VHDL syntax error at Alu.vhd(64) near text ")";  expecting ":", or ","
Error (10500): VHDL syntax error at Alu.vhd(65) near text ")";  expecting ":", or ","

我试图纠正它们,但是看起来有些错误没有意义,因为我具有错误显示的所有标点符号。此外,我已将文件设置为上层实体。

1 个答案:

答案 0 :(得分:2)

您的代码中仍然存在一些语法错误。您应该可以自己解决它们,但我要注意一些注意事项:

  1. 在包主体内部声明一个过程应该以例如procedure add(...) is。该行不应以半彩色结尾,您已使用函数正确完成了此操作。

  2. 使用表达式(size-1 downto 0)=> "1",您可能想制作一个大小为“ size”的向量,仅包含1s?为此,请使用表达式,例如x1'range => '1',其中x1可以是大小为size的向量变量。

  3. 对于未定义的+类型,您可以使用bit_vector运算符。您可能打算使用std_logic_vector类型,因为您导入了ieee.std_logic_unsigned.all。或者使用numeric_bit_unsigned包。

    顺便说一句。此包不受支持,因此您可能希望通过转换为unsigned来更改数据类型并改用ieee.numeric_std.all包。

  4. 未声明的类型等可能存在错误。请检查如何使用use语句。

还有其他一些小的语法错误(我认为还有一些逻辑错误),但是在修复这些错误之后,您应该能够通过阅读错误消息来解决它们。