Question

我正在运行VHDL代码但是在编译时我在端口映射行遇到了错误。有什么问题，如何解决？

错误在于：

错误（10500）：DU.vhd（52）处文本“port”附近的VHDL语法错误;期待“（”，“或”，“或”。“

我的代码：

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity DU is
    port(
    Clk     : in std_logic;
    state   : in std_logic_vector (3 downto 0);     
    Input   : in std_logic_vector (63 downto 0);
    De_out,En_out       : out std_logic_vector (63 downto 0)
    );
end DU;

architecture result of DU is
signal en_data1,en_data2    : std_logic_vector (63 downto 0);
signal de_data1,de_data2    : std_logic_vector (63 downto 0);
signal en_sum,de_sum        : std_logic_vector (31 downto 0):=x"00000000";
signal k0,k1,k2,k3,delta    : std_logic_vector (31 downto 0);

component encoder
port(
    k0,k1,k2,k3,delta   : in std_logic_vector (31 downto 0);
    En_In   : in std_logic_vector (63 downto 0);
    En_Out  : out std_logic_vector (63 downto 0)
);
end component;

component decoder
port(
    k0,k1,k2,k3,delta   : in std_logic_vector (31 downto 0);
    Dec_In  : in std_logic_vector (63 downto 0);
    Dec_Out : out std_logic_vector (63 downto 0)
);
end component;


begin
    process(state,Clk)
    begin
    k0 <= x"CBE6160F";
    k1 <= x"12345678";
    k2 <= x"FC189540";
    k3 <= x"00AB7655";
    delta <= x"9E3779B9";

    if(rising_edge(Clk)) then
        if state(0) = '1' then
            en_data1 <= Input;
            en_sum <= en_sum + delta;
            En_Out <= Input;
        elsif state(1) = '1' then
            encryption : encoder port map (k0,k1,k2,k3,en_sum,en_data1,en_data2);
            En_Out <= en_data2;
            en_data1 <= en_data2;
            en_sum <= en_sum + delta;
        elsif state(2) = '1' then
            de_data1 <= en_data2;
            de_sum <= en_sum;
            De_Out <= de_data1;
        elsif state(3) = '1' then
            decryption : decoder port map (k0,k1,k2,k3,de_sum,de_data1,de_data2);
            De_Out <= de_data2;
            de_data1 <= de_data2;
            de_sum <= de_sum - delta;
        end if;
    end if;
    end process;

end result;

Answer 1

您无法在流程中实例化实体。

encryption : encoder port map (k0,k1,k2,k3,en_sum,en_data1,en_data2);

这需要在您的流程之外完成，输入连接无论状态如何。然后，您可以根据您所处的状态对输出进行多路复用。

运行vhdl代码时出错

1 个答案: