Question

我正在尝试创建一个十六进制到七段编码器。当我合成时，我在每行上都有错误，我有一个if语句，我无法弄清楚原因。如果有人能指出我正确的方向，我会非常感激！

architecture Behavioral of encoder is
begin
CASE hex IS
  WHEN "0000" =>
    a <= '1';
    b <= '1';
    c <= '1';
    d <= '1';
    e <= '1';
    f <= '1';
    g <= '0';
...

Answer 1

您不能在流程之外使用案例结构。

如果你想要一个案例结构，你会写：

process (hex)
begin
  CASE hex IS
    WHEN "0000" =>
      a <= '1';
      b <= '1';
      c <= '1';
      d <= '1';
      e <= '1';
      f <= '1';
      g <= '0';
    WHEN ...
    WHEN ...
    WHEN others =>
      a <= '0'
      b <= '0'
      etc...
end process

或者，您可以在进程外使用when / else。但是，您可能会将值分配给矢量，然后将其拆分，如下所示：

在架构中：

signal sevseg : std_logic_vector(6 downto 0)

并在rtl部分：

bcd <= "0000000" when hex = "0000" else
       "0011010" when hex = "0001" else
       ...
       "0011110" when hex = "0010" else
       "0000000"

a <= sevseg(0)
b <= sevseg(1)
c <= sevseg(2)
d <= sevseg(2)
...

进程外的另一个选项是with / select语句：

with hex select sevseg <=
  "0000000" when "0000",
  "0001010" when "0001",
  ...

然后你需要再次将bcd分成a，b，c等。如上例所示。

Answer 2

除了anderswb之外还有完整性答案：

还宣布了一个子程序，在这种情况下是一个函数，在这里显示为一个实体声明项，其中任何一个实体的架构都可以使用它：

library ieee;
use ieee.std_logic_1164.all;

entity hex_7seg is
    port ( 
        clk:        in  std_logic;
        val:        in  std_logic_vector (31 downto 0);
        anode:      out std_logic_vector (7 downto 0);
        segment:    out std_logic_vector (6 downto 0)
    );

    --  seven segment display
    --  
    --        a
    --     f      b
    --        g
    --     e      c
    --        d
    --
    --  SEGMENT is defined (g downto a)
    --
   function HEX_TO_7SEG (bcd: std_logic_vector(3 downto 0))
       return std_logic_vector is
   begin
       case bcd is
           when "0000" => return "1000000"; -- 0
           when "0001" => return "1111001"; -- 1
           when "0010" => return "0100100"; -- 2
           when "0011" => return "0110000"; -- 3
           when "0100" => return "0011001"; -- 4
           when "0101" => return "0010010"; -- 5
           when "0110" => return "0000010"; -- 6
           when "0111" => return "1111000"; -- 7
           when "1000" => return "0000000"; -- 8
           when "1001" => return "0011000"; -- 9
           when "1010" => return "0001000"; -- A
           when "1011" => return "0000011"; -- b
           when "1100" => return "0111001"; -- C
           when "1101" => return "0100001"; -- d
           when "1110" => return "0000110"; -- E
           when "1111" => return "0001110"; -- F
           when others => return "XXXXXXX"; -- does not synthesize
       end case;
   end function;
end entity;

还使用具有十六进制值的ROM作为索引：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity hex_7seg is
    port ( 
        clk:        in  std_logic;
        val:        in  std_logic_vector (31 downto 0);
        anode:      out std_logic_vector (7 downto 0);
        segment:    out std_logic_vector (6 downto 0)
    );

    --  seven segment display
    --  
    --        a
    --     f      b
    --        g
    --     e      c
    --        d
    --
    --  SEGMENT is defined (g downto a)
    --
    type segment7 is array (integer range 0 to 15) of 
                    std_logic_vector (6 downto 0);

    constant hex_to_segment: segment7 := (
                 "1000000", -- 0
                 "1111001", -- 1
                 "0100100", -- 2
                 "0110000", -- 3
                 "0011001", -- 4
                 "0010010", -- 5
                 "0000010", -- 6
                 "1111000", -- 7
                 "0000000", -- 8
                 "0011000", -- 9
                 "0001000", -- A
                 "0000011", -- b
                 "0111001", -- C
                 "0100001", -- d
                 "0000110", -- E
                 "0001110"  -- F
             );
end entity;

architecture foo of hex_7seg is
    signal seg7_val: integer range 0 to 15;
    signal hex:      std_logic_vector (3 downto 0);
begin
    seg7_val <= to_integer(unsigned(hex));

    segment <= hex_to_segment(seg7_val);
end architecture;

请注意，函数调用是一个表达式，因为它是一个索引数组值，这意味着它们可以在并发或顺序语句中使用。

如果您分析，详细说明并运行上述实体/体系结构对，您会发现从包含numeric_std metavalue detected, returning 0的包中获取to_integer的报告声明，因为hex已初始化为所有X＆＃ 39; S。在数组类型和数字标量类型之间使用转换例程时，在声明中间信号或变量时提供默认值可以防止这种情况发生。

具有时间状态的十六进制到7段编码器语法错误

2 个答案: