VHDL类型的变量与函数调用的类型不兼容

Question

我正在尝试使用vhdl中的函数返回4个整数的数组。我的代码中除以下内容外没有语法错误：持有人类型与加密类型不兼容。

  type matrix1x4 is array (0 to 3) of integer;
begin
  input <= digit1 & digit2;
process(digit1,digit2)
    begin
        encryptFlag <= '0';
        decryptFlag <= '0';
        input <= digit1 & digit2;
        O <= input;
end process;

process(encry)

    variable holder: matrix1x4;
    begin
        if encryptFlag = '0' and encry = '1' then
            encryptFlag <= '1'; 
            decryptFlag <= '1';
            holder := encryption(input);

程序包中保存我的函数加密的代码：

    type matrix1x2 is array (0 to 1) of integer;
type matrix1x4 is array (0 to 3) of integer;
type matrix2x2 is array (1 to 2, 1 to 2) of integer;
function encryption (input: std_logic_vector(7 downto 0)) return 
             matrix1x4;

我的加密功能中的代码：

    variable s1, s2: std_logic_vector(3 downto 0);
variable char1, char2: character;
variable int1, int2,temp1,temp2: integer;
variable inputMat: matrix1x2;
variable encodeMat: matrix2x2;
variable O: matrix1x4;
begin
    s1 := input(7 downto 4);
    char1 := binToChar(s1);
    int1 := charToInt(char1);
    s2 := input(3 downto 0);
    char2 := binToChar(s2);
    int2 := charToInt(char2);
    inputMat:= (int1,int2);
    encodeMat:= ((1,1),(3,4));
    temp1 := inputMat(0) * encodeMat(1,1) + inputMat(1) * encodeMat(1,2);
    temp2 := inputMat(1) * encodeMat(2,1) + inputMat(0) * encodeMat(2,2);
    int1    := temp1;
    int2    := temp2;
    temp1 := (temp1 mod 16) + 1;
    temp2 := (temp2 mod 16) + 1;
    O :=  (int1,int2, temp1, temp2);
return O;