Question

Ich有两种不同的类型：

type signal_4bit_t is
record
   signals_v      : STD_ULOGIC_VECTOR (3 downto 0);
end record;

 type signal_8bit_t is
record
   signals_v      : STD_ULOGIC_VECTOR (7 downto 0);
end record;

我创建了两个数组：

 type Array_signal_4bit_t   is array (0 to 2) of signal_4bit_t;
 type Array_signal_8bit_t   is array (0 to 2) of signal_8bit_t;

并且一个实体使用4位数组作为输入：

entity test_input is
    Port ( 
           hx_i      : in  Array_signal_4bit_t;
           lx_i      : in  Array_signal_4bit_t;
          );
end test;

和另一个使用8位数组作为输出：

entity test_ouput is
    Port ( 
           out_o      : out Array_signal_8bit_t
          );
end test;

对于两个组件之间的一致性，我使用信号：

signal tets_out_to_test_in   : Array_signal_8bit_t;

瞬间看起来像这样：

in: test_input 
    Port Map ( 
           hx_i  =>    tets_out_to_test_in(7 downto 4),
           lx_i  =>    tets_out_to_test_in(3 downto 0)
          );

out: test_out 
    Port Map ( 
           out_o  =>    tets_out_to_test_in
          );

现在我收到错误“hx_i的类型与tets_out_to_test_in的类型不兼容。我看到Array_signal_4bit_t与Array_signal_8bit_t不同，但是有一种”简单“的方法来修复这个问题而不需要我的entites吗？或者任何想法如何我可以解决这个问题吗？

Answer 1

您的代码有两个问题：

您必须解决记录成员才能访问内部std_ulogic_vectors。
您必须循环遍历向量test_out_to_test_in的每个索引，以将其分配给结果向量。这可以通过生成语句或进程（不是很好的解决方案）或函数（很好的解决方案）来完成。

信号：

signal test_out_to_test_in   : Array_signal_8bit_t;
signal test_in_lo            : Array_signal_4bit_t;
signal test_in_hi            : Array_signal_4bit_t;

实例：

out: test_out 
  Port Map ( 
    out_o  =>  test_out_to_test_in
  );

gen : for i in test_out_to_test_in'range generate
  test_in_lo(i).signals_v   <= test_out_to_test_in(i).signals_v(3 downto 0);
  test_in_hi(i).signals_v   <= test_out_to_test_in(i).signals_v(7 downto 4);
end generate;

in: test_input 
  Port Map ( 
    hx_i  =>    test_in_hi,
    lx_i  =>    test_in_lo
  );

您确定要使用记录，甚至不是子类型吗？

修改1：

如果你只是想创建一个4比特的std_ulogic_vector的新类型，你可以使用一个子类型：

subtype signal_4bit_t is STD_ULOGIC_VECTOR (3 downto 0);
subtype signal_8bit_t is STD_ULOGIC_VECTOR (7 downto 0);

在大多数情况下，让数组类型不受限制更灵活：

type Array_signal_4bit_t is array (NATURAL range <>) of signal_4bit_t;
type Array_signal_8bit_t is array (NATURAL range <>) of signal_8bit_t;

现在您的作业代码如下所示：

signal test_out_to_test_in   : Array_signal_8bit_t(0 to 2);
signal test_in_lo            : Array_signal_4bit_t(0 to 2);
signal test_in_hi            : Array_signal_4bit_t(0 to 2);

out: test_out 
  Port Map ( 
    out_o  =>  test_out_to_test_in
  );

gen : for i in test_out_to_test_in'range generate
  test_in_lo(i)   <= test_out_to_test_in(i)(3 downto 0);
  test_in_hi(i)   <= test_out_to_test_in(i)(7 downto 4);
end generate;

in: test_input 
  Port Map ( 
    hx_i  =>    test_in_hi,
    lx_i  =>    test_in_lo
  );

编辑2：

您可以通过编写函数隐藏转换代码（现在使用生成语句）：

function to_4bit_hi(value : Array_signal_8bit_t) return Array_signal_4bit_t is
  variable Result : Array_signal_4bit_t;
begin
  for i in value'range loop
    Result(i) <= value(i)(7 downto 4);
  end loop;
  return Result;
end function;

您需要3 downto 0的第二个函数，或者将偏移量作为参数传递给函数。每个工具都不支持在端口映射中使用函数，因此您仍需要两个额外的信号。

signal test_out_to_test_in   : Array_signal_8bit_t(0 to 2);
signal test_in_lo            : Array_signal_4bit_t(0 to 2);
signal test_in_hi            : Array_signal_4bit_t(0 to 2);

out: test_out 
  Port Map ( 
    out_o  =>  test_out_to_test_in
  );

test_in_lo   <= to_4bit_lo(test_out_to_test_in);
test_in_hi   <= to_4bit_hi(test_out_to_test_in);

in: test_input 
  Port Map ( 
    hx_i  =>    test_in_hi,
    lx_i  =>    test_in_lo
  );

如果您对更多矢量操作函数和程序感兴趣，请查看此包：https://code.google.com/p/picoblaze-library/source/browse/vhdl/lib_PoC/vectors.vhdl?name=release

Answer 2

创建最小，可验证和完整的示例：

library ieee;
use ieee.std_logic_1164.all;

package somepack is
    type signal_4bit_t is
    record
       signals_v      : std_ulogic_vector (3 downto 0);
    end record;

     type signal_8bit_t is
    record
       signals_v      : std_ulogic_vector (7 downto 0);
    end record;
    type array_signal_4bit_t   is array (0 to 2) of signal_4bit_t;
    type array_signal_8bit_t   is array (0 to 2) of signal_8bit_t;
end package;

use work.somepack.all;
entity test_input is
    port ( 
           hx_i      : in  array_signal_4bit_t;
           lx_i      : in  array_signal_4bit_t
         );
end test_input;

architecture foo of test_input is
begin
end architecture;

use work.somepack.all;
entity test_output is
    port ( 
           out_o      : out array_signal_8bit_t
         );
end test_output;

architecture foo of test_output is
begin
end architecture;

library ieee;
use ieee.std_logic_1164.all;
use work.somepack.all;

entity sometestbench is
end entity;

architecture foo of sometestbench is
    signal tets_out_to_test_in: array_signal_8bit_t;
    component test_input is
        port (
            hx_i: in  array_signal_4bit_t;
            lx_i: in  array_signal_4bit_t
        );
    end component;
    component test_output is
        port (
           out_o      : out array_signal_8bit_t        
        );
    end component;    

    signal hx_i_high: array_signal_4bit_t;
    signal lx_i_low:  array_signal_4bit_t;

begin

    hx_i_high(0).signals_v <= tets_out_to_test_in(0).signals_v(7 downto 4);
    hx_i_high(1).signals_v <= tets_out_to_test_in(1).signals_v(7 downto 4);
    hx_i_high(2).signals_v <= tets_out_to_test_in(2).signals_v(7 downto 4);
    lx_i_low(0).signals_v  <= tets_out_to_test_in(0).signals_v(3 downto 0);
    lx_i_low(1).signals_v  <= tets_out_to_test_in(1).signals_v(3 downto 0);
    lx_i_low(2).signals_v  <= tets_out_to_test_in(2).signals_v(3 downto 0);                

label_in: test_input 
    port map ( 
          --  hx_i  =>    tets_out_to_test_in(7 downto 4),
          hx_i => hx_i_high,
          --lx_i  =>    tets_out_to_test_in(3 downto 0)
          lx_i => lx_i_low
    );


label_out: test_output 
    port map ( 
           out_o  =>    tets_out_to_test_in
          );    
end architecture;

存在各种标点问题和拼写错配，进出不能用作标识符（标签），它们是保留字。组件test_out应该是test_output，...

还有一些更直接的，从array_signal_8bit_t类型中提取的元素构造array_signal_4bit_t类型：

    hx_i_high <= array_signal_4bit_t'(
               0 => (signals_v => tets_out_to_test_in(0).signals_v(7 downto 4)),
               1 => (signals_v => tets_out_to_test_in(1).signals_v(7 downto 4)),
               2 => (signals_v => tets_out_to_test_in(2).signals_v(7 downto 4))
               );

    lx_i_low <= array_signal_4bit_t'(
               0 => (signals_v => tets_out_to_test_in(0).signals_v(3 downto 0)),
               1 => (signals_v => tets_out_to_test_in(1).signals_v(3 downto 0)),
               2 => (signals_v => tets_out_to_test_in(2).signals_v(3 downto 0))
               );

您不能在关联列表中实际执行此操作，因为限定表达式的表达式操作数必须是全局静态的（历史上（ - 1993），并且可能仍然用于合成）。（在IEEE Std 1076-2008,6.5.6.3端口条款中，第6段）：

如果块的正式端口的给定关联元素的实际部分是保留字惯性，后跟表达式，或者是非全局静态的表达式，那么给定的关联element等效于端口与在声明区域中隐式声明的匿名信号的关联，该声明区域立即封闭该块。该信号与正式端口具有相同的子类型，并且是
形式的隐式并发信号赋值语句的目标

anonymous <= E;

其中E是给定关联元素的实际部分中的表达式。并发信号赋值语句出现在与块相同的语句部分中。

以上示例也说明了您不必拥有循环。

这个MVCe分析，阐述和模拟（虽然没有做任何特别有趣的事情）。

略有不同的架构使用过程：

architecture fie of sometestbench is
    signal tets_out_to_test_in: array_signal_8bit_t;
    component test_input is
        port (
            hx_i: in  array_signal_4bit_t;
            lx_i: in  array_signal_4bit_t
        );
    end component;
    component test_output is
        port (
           out_o      : out array_signal_8bit_t        
        );
    end component;    

    signal hx_i_high: array_signal_4bit_t;
    signal lx_i_low:  array_signal_4bit_t;

    procedure slice_array_signal_8bit (
            signal input:   in  array_signal_8bit_t; 
            signal low:     out array_signal_4bit_t;
            signal high:    out array_signal_4bit_t
    ) is
    begin
        for i in array_signal_4bit_t'range loop
            high(i).signals_v <= input(i).signals_v(7 downto 4);
            low(i).signals_v  <= input(i).signals_v(3 downto 0);
        end loop;
    end procedure;

begin

BREAKOUT: 
slice_array_signal_8bit ( tets_out_to_test_in, hx_i_high, lx_i_low);             

label_in: test_input 
    port map ( 
          hx_i => hx_i_high,
          lx_i => lx_i_low
    );


label_out: test_output 
    port map ( 
           out_o  =>    tets_out_to_test_in
          );    
end architecture;

其中还告诉我们如何使用流程声明：

architecture foe of sometestbench is
    signal tets_out_to_test_in: array_signal_8bit_t;
    component test_input is
        port (
            hx_i: in  array_signal_4bit_t;
            lx_i: in  array_signal_4bit_t
        );
    end component;
    component test_output is
        port (
           out_o      : out array_signal_8bit_t        
        );
    end component;    

    signal hx_i_high: array_signal_4bit_t;
    signal lx_i_low:  array_signal_4bit_t;

begin

BREAKOUT: 
    process (tets_out_to_test_in)
    begin
        for i in array_signal_4bit_t'range loop
            hx_i_high(i).signals_v <= tets_out_to_test_in(i).signals_v(7 downto 4);
            lx_i_low(i).signals_v  <= tets_out_to_test_in(i).signals_v(3 downto 0);
        end loop;
    end process;          

label_in: test_input 
    port map ( 
          hx_i => hx_i_high,
          lx_i => lx_i_low
    );


label_out: test_output 
    port map ( 
           out_o  =>    tets_out_to_test_in
          );    
end architecture;

最后，最简单的方法：

architecture fum of sometestbench is
    signal tets_out_to_test_in: array_signal_8bit_t;
    component test_input is
        port (
            hx_i: in  array_signal_4bit_t;
            lx_i: in  array_signal_4bit_t
        );
    end component;
    component test_output is
        port (
           out_o      : out array_signal_8bit_t
        );
    end component;
begin

label_in: test_input
    port map (
          hx_i(0).signals_v => tets_out_to_test_in(0).signals_v(7 downto 4),
          hx_i(1).signals_v => tets_out_to_test_in(1).signals_v(7 downto 4),
          hx_i(2).signals_v => tets_out_to_test_in(2).signals_v(7 downto 4),
          lx_i(0).signals_v => tets_out_to_test_in(0).signals_v(3 downto 0),
          lx_i(1).signals_v => tets_out_to_test_in(1).signals_v(3 downto 0),
          lx_i(2).signals_v => tets_out_to_test_in(2).signals_v(3 downto 0)
    );

label_out: test_output
    port map (
           out_o  =>    tets_out_to_test_in
          );
end architecture;

我们可以在端口关联列表中将formal的复合类型元素分别映射到实际元素。这个表格应该是合成资格。

VHDL的xxx类型与xxx的类型不兼容

2 个答案: