Vivado行为模拟显示未定义（XX）输出

Question

我正在尝试在Vivado中对我的Verilog代码进行行为模拟，但是在模拟运行而不是获取输出之后，它们显示为带有XX的红线，我认为这是未定义的

我试图更改Verilog文件顶部的时间刻度，如Xilinx论坛帖子中所示，但这不能解决我的问题。

这是我的Verilog程序：

module ctrl(
    input clk,
    input [5:0] A,
    input [5:0] B,
    input [3:0] C,
    output reg [6:0] led
    ); 
    always @(posedge clk)
    begin
        case(C)
            4'b0000:
                //A + B
                led <= A + B;
            4'b0001:
                //A - B
                led <= A - B;
            4'b0010:
                //A++
                led <= A + 1'b1;
            4'b0011:
                //A--
                led <= A - 1'b1;
            4'b0100:
                //B++
                led <= B + 1'b1;
            4'b0101:
                //B--
                led <= B - 1'b1;
            4'b0110:
                //A & B
                led = (A & B);
            4'b0111:
                //A | B
                led = (A | B);                
            4'b1000:
                //A ^ B
                led = (A ^ B);
            4'b1001:
                //~A
                led = {1'b0,~A[5:0]
            4'b1010:
                //~B
                led = {1'b0,~B[5:0]};
            4'b1011:
                //A << B
                led = A << B;
            4'b1100:
                //B << A
                led = B << A;

            4'b1101:
                //Light LED[0] if A > B
                if(A > B)
                    led = 7'b0000001;
                else
                    led = 7'b0000000;
            4'b1110:
                //Light LED[0] if A < B
                if(A < B)
                    led = 7'b00000001;
                else
                    led = 7'b0000000;

            4'b1111:
                //Light LED[0] if A=B
                if(A == B)
                    led = 7'b0000001;
                else
                    led = 7'b0000000;          
            default: 
                //Unimplemented opcode
                led <= 7'b1111111;
        endcase
    end
endmodule

测试台

module ctrl_testbench();


    reg[5:0] A;
    reg[5:0] B;
    reg[3:0] C;
    wire[6:0] led;

    ctrl dut (
        .A(A),
        .B(B),
        .C(C),
        .led(led)
    );

    initial begin
        A = 6'b000001;
        B = 6'b000001;
        C = 4'b0000;
        #100;
        A = 6'b000000;
        B = 6'b000000;
        C = 4'b0000;
        #100;
        A = 6'b000010;
        B = 6'b000010;
        C = 4'b0001;
    end
endmodule

运行行为仿真之后，时序图给出了这一点。如您所见，A-C（输入）已正确填充，但是LED（输出）为红色，并显示XX。

我正在尝试显示实际输出

Answer 1

您需要创建一个时钟信号并驱动DUT的clk输入：

module ctrl_testbench();
    reg[5:0] A;
    reg[5:0] B;
    reg[3:0] C;
    wire[6:0] led;
    reg clk;

    initial begin
        clk = 0;
        forever #5 clk = ~clk;
    end

    ctrl dut (
        .clk(clk),
        .A(A),
        .B(B),
        .C(C),
        .led(led)
    );

    initial begin
        A = 6'b000001;
        B = 6'b000001;
        C = 4'b0000;
        #100;
        A = 6'b000000;
        B = 6'b000000;
        C = 4'b0000;
        #100;
        A = 6'b000010;
        B = 6'b000010;
        C = 4'b0001;
        $finish;
    end
endmodule