由于我无法检查它,所以我想问一下这段vhdl代码是否可以编译。
我在大学里做了一个项目,其中一部分是从BCD到七段显示器的转换器。我需要它具有四个输入和四个输出(四个数字),但是那时候我没有太多的语言知识和经验,并且在一种体系结构中我基本上使用相同的代码四次。
我现在想使它更具可读性和“专业性”,因此我决定使用一种过程来避免多次重复相同的行。问题是,我无法对其进行测试。
我在线搜索了过程语法,并根据新知识对代码进行了改进。这是现在的样子。
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_unsigned.all;
entity BCDto7SEGconverter is
port(
sec_j: in std_logic_vector( 3 downto 0 );
sec_d: in std_logic_vector( 3 downto 0 );
min_j: in std_logic_vector( 3 downto 0 );
min_d: in std_logic_vector( 3 downto 0 );
sec_j_7seg: out std_logic_vector( 6 downto 0 );
sec_d_7seg: out std_logic_vector( 6 downto 0 );
min_j_7seg: out std_logic_vector( 6 downto 0 );
min_d_7seg: out std_logic_vector( 6 downto 0 ) );
end BCDto7SEGconverter;
architecture convert of bcdto7SEGconverter is
begin
procedure change(
signal r_IN : in std_logic_vector( 3 downto 0 );
signal r_OUT : out std_logic_vector( 3 downto 0 )
) is
begin
case r_iN is
when "0000" => r_OUT <= "1000000";
when "0001" => r_OUT <= "1111001";
when "0010" => r_OUT <= "0100100";
when "0011" => r_OUT <= "0110000";
when "0100" => r_OUT <= "0011001";
when "0101" => r_OUT <= "0010010";
when "0110" => r_OUT <= "0000010";
when "0111" => r_OUT <= "1111000";
when "1000" => r_OUT <= "0000000";
when "1001" => r_OUT <= "0010000";
when others => r_OUT <= "1111111";
end case;
end procedure;
begin
process( sec_j, sec_d, min_j, min_d )
begin
change(sec_j,sec_j_7seg);
change(sec_d,sec_d_7seg);
change(min_j,min_j_7seg);
change(min_d,min_d_7seg);
end process;
end convert;
我自己无法编译此代码,所以我想知道这段代码是否可以编译。