仅在Modelsim上出现未知标识符错误?

时间:2018-12-24 16:20:20

标签: vhdl

我有以下HDL描述,该描述可在Quartus中成功编译,但在Modelsim中却出现错误。

我尝试仅使用std_logic_vector来编写代码,但没有成功。

library ieee;
use ieee.std_logic_1164.all;
use work.all;
use ieee.numeric_std.all;


entity upcounter is
port(
S,NF : in  std_logic_unsigned (2 downto 0);
O : out  std_logic_unsigned (2 downto 0));

end upcounter;


architecture struct of upcounter is
begin 

if (S < NF) then
countup: while (S < NF) loop
S <= S + '1';
end loop countup;
else 

countdown: while (S > NF) loop
 S <= S - '1';
 end loop countdown;
 end if;


  O <= S;

 end struct;

0 个答案:

没有答案