我在modelim 10.4中遇到以下错误:
错误:(vlog-13069)D:/ divya / verilog /流水线alu / alu.v(5):附近“ =”:语法错误,意外的'=',期望IDENTIFIER或TYPE_IDENTIFIER或NETTYPE_IDENTIFIER。
代码:
module func(output reg[15:0] out,input[15:0] a,b,input[3:0] select);
case(select)
0:out=a+b;
1:out=a-b;
2:out=a*b;
3:out=a;
4:out=b;
5:out=a&b;
6:out=a|b;
7:out=a^b;
8:out=~a;
9:out=~b;
10:out=a>>1;
11:out=a<<1;
default:out=16'hxxxx;
endcase
endmodule
答案 0 :(得分:0)
在实现上述组合逻辑时,需要确保将功能描述放在程序块中,例如always @(*)
或assign
语句中(使用哪种取决于?逻辑长度和其他次要因素)。以下是您的代码,其中包含一些格式设置(请记住,编码风格不仅仅在于美观;它还可以帮助您发现错误并简化代码的读取!):
module func(output reg [15:0] out,
input [15:0] a, b,
input [3:0] select); // I like to break up io on multiple lines to make it easier to read
always @(*) begin // Need to put logic in a procedural block!
case(select)
0: out = a + b;
1: out = a - b;
2: out = a * b; // Note that this would take quite a bit of logic compared to all the other operations here, combinational multiply take alot of gates
3: out = a;
4: out = b;
5: out = a & b;
6: out = a | b;
7: out = a ^ b;
8: out = ~a;
9: out = ~b;
10: out = a >> 1;
11: out = a << 1;
default: out = 16'hxxxx;
endcase
end
endmodule