UVM - 错误 - 接近":":语法错误,意外':',期待IDENTIFIER或时钟

时间:2016-12-14 09:44:29

标签: macros system-verilog uvm

我创建了自己的my_macros文件:

`ifndef MY_MACROS_SV
`define MY_MACROS_SV

// MACRO: 'my_fatal_err
// calls uvm_fatal in case the assertion is not correct
`define my_fatal(condition, msg )\
   assert (condition) else\
`uvm_fatal("FATAL ERROR", msg)\
\
`define add_rand(mem_type, mem)\
   case (mem_type)\
     "int": add_rand_int(mem);\
     "bit": add_rand_bit(mem);\    
     default: `uvm_fatal("FATAL ERROR", "type is not supported")\ 
     endcase  



`endif  //MY_MACROS_SV

mem_type期望string和mem是类的成员。 我收到以下编译错误: at .. \ sv \ my_macros.sv(19):near":&#34 ;:语法错误,意外':',期待IDENTIFIER或时钟。

*第19行是"默认:...."

1 个答案:

答案 0 :(得分:0)

分开你的2个宏:

`ifndef MY_MACROS_SV
`define MY_MACROS_SV

// MACRO: 'my_fatal_err
// calls uvm_fatal in case the assertion is not correct
`define my_fatal(condition, msg )\
   assert (condition) else\
`uvm_fatal("FATAL ERROR", msg)

`define add_rand(mem_type, mem)\
   case (mem_type)\
     "int": add_rand_int(mem);\
     "bit": add_rand_bit(mem);\    
     default: `uvm_fatal("FATAL ERROR", "type is not supported")\ 
     endcase  



`endif  //MY_MACROS_SV