使用局部参数SystemVerilog访问generate的迭代周期

Question

def callable(i_e_, some_kind_of_function): # real signature unknown; restored from __doc__
    """
    Return whether the object is callable (i.e., some kind of function).

    Note that classes are callable, as are instances of classes with a
    __call__() method.
    """
    pass

当我尝试访问“到”列表时：

    localparam [32*3*60-1:0] param_t = 
    {
        32'h1,32'hFFFF_FFFF,32'b1,
        32'h2,32'hFFFF_FFFF,32'b1,
        32'h3,32'hFFFF_FFFF,32'b1,
        32'h4,32'hFFFF_FFFF,32'b1 
    };

genvar i;
generate for(i = 0; i < 60; i = i + 1 ) 
begin : list 
    localparam [((32)*3)-1:0] temp = param_t[i*32+:32]; 
    localparam [(32)-1:0]     Ap   = temp[(32*3)-1:(32*2)]; 
    localparam [(32)-1:0]     Bp   = temp[(32*2)-1:(32)]; 
    localparam [(32)-1:0]     Cp   = temp[(32)-1:0]; 
end

我得到一个错误：

wire [31:0] test = list[0].Ap;

当我使用XST时，该区域没有问题。 这是针对SystemVerilog的Veriog代码的重用。我想保持向后兼容性。