Question

我正在编码3位ALU。我遇到的问题是当Opcode =“ 001”时的乘法器。我正在尝试添加3 bit_vectors（5降至0），并且抛出错误“运算符“ +”找到'0'定义”。我环顾四周，发现了一些链接found '0' definitions of operator "+" in VHDL，但是添加任何软件包似乎都无法为我解决错误。

此外，我在某处读到，因为您正在用VHDL编码硬件，所以最好记住增量延迟。由于我要在过程中为信号分配值，因此输出最终产品是否真的起作用？否则增量延迟会导致信号在暂停过程之前不会更新。

在操作码=“ 001”的块中，错误发生在第67行“ Z <= t4 + t5 + t6”。谢谢任何能提供一些建议的人。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity ALU is
    PORT(
        X,Y   : IN BIT_VECTOR(2 downto 0);
        Opcode : IN BIT_VECTOR(2 downto 0);
        Z      : OUT BIT_VECTOR(5 downto 0);
        CLK   : IN BIT
        );
end ALU;

architecture Behavioral of ALU is
   COMPONENT adder3 is
     PORT (
       A1 ,A2, A3, B1, B2, B3, Cin : IN BIT ;
       Sum1 ,Sum2,  Sum3, Cout : OUT BIT );
    END COMPONENT;

        SIGNAL adder_output: BIT_VECTOR(3 downto 0);
        SIGNAL temp: BIT_VECTOR(2 downto 0);
        SIGNAL t1,t2,t3: BIT_VECTOR(2 downto 0);
        SIGNAL t4,t5,t6: BIT_VECTOR(5 downto 0);
begin

    ADD3: adder3 PORT MAP(
        A1 => X(0),
        B1 => Y(0),
        A2 => X(1),
        B2 => Y(1),
        A3 => X(2),
        B3 => Y(2),
        Cin => '0',
        Sum1 => adder_output(0),
        Sum2 => adder_output(1),
        Sum3 => adder_output(2),
        Cout => adder_output(3)
        );

    PROCESS(X, Y, CLK, Opcode)
        BEGIN
            IF(CLK'EVENT AND CLK='1')THEN
                IF Opcode = "000" THEN
                    Z <= adder_output;
                ELSIF Opcode = "001" THEN
                    IF Y(0) = '1' THEN
                        t1 <= X;
                    ELSE
                        t1 <= "000";
                    END IF;
                    IF Y(1) = '1' THEN
                        t2 <= X;
                    ELSE
                        t2 <= "000";
                    END IF;
                    IF Y(2) = '1' THEN
                        t3 <= X;
                    ELSE
                        t3 <= "000";
                    END IF;
                     t4 <= "000"&t1;
                     t5 <= "00"&t2&"0";
                     t6 <= "0"&t3&"00";
                     Z <= t4+t5+t6;
                ELSIF Opcode = "010" THEN
                    Z <= X AND Y;
                ELSIF Opcode = "011" THEN
                    Z <= X OR Y;
                ELSIF Opcode = "100" THEN
                    Z <= X XOR Y;
                ELSIF Opcode = "101" THEN
                    temp <= NOT X;
                    Z <= "000"&temp;
                ELSIF Opcode = "110" THEN
                    IF Y = "000" THEN
                        Z <= "000"&X(2 downto 0);
                    ELSIF Y = "001" THEN
                        Z <= "00"&X(2 downto 0)&"0";
                    ELSIF Y = "010" THEN
                        Z <= "0"&X(2 downto 0)&"00";
                    ELSIF Y = "011" THEN
                        Z <= X(2 downto 0)&"000";
                    ELSIF Y = "100" THEN
                         Z <= X(1 downto 0)&"0000";
                    ELSIF Y = "101" THEN
                         Z <= X(0)&"00000";
                    ELSE
                         Z <= "000000";
                    END IF;
                ELSE
                    IF Y = "000" THEN
                        Z <= "000"&X(2 downto 0);
                    ELSIF Y = "001" THEN
                        Z <= "0000"&X(2 downto 1);
                    ELSIF Y = "010" THEN
                        Z <= "00000"&X(2);
                    ELSE
                        Z <= "000000";
                    END IF;
                END IF;
           END IF;            
       END PROCESS;
end Behavioral;

Answer 1

如果要对bit_vector进行无符号算术，则需要使用VHDL 2008规范中的numeric_bit_unsigned库。对于有符号算术，您需要使用numeric_std或numeric_bit中的无符号或有符号类型（唯一的区别是基本类型）。

为什么在添加bit_vector时得到“找到的运算符“ +”的'0'定义”？ Delta延误是一个因素吗？

1 个答案: