VHDL无法确定运营商的定义' ='' - 找到0个定义

时间:2014-11-30 20:25:03

标签: vhdl

case state is  
    when (state = 0) =>     
        win <= 0;
        stand <= 0;
        bust <= 0;
        hit <=0;
        state <= "1";

我的when (state = 0) =>有错误。任何帮助表示赞赏。

2 个答案:

答案 0 :(得分:1)

这里有两个问题:
你的案例陈述在语法上是不正确的。使用when 0 =>代替when (state = 0) => 你能告诉我们state的宣言是什么样的吗?看起来您已将state声明为std_logic_vector,但将其与整数0进行比较,或者您已将state声明为整数并指定std_logic_vector它。

答案 1 :(得分:0)

状态机的基本模板(2处理方式)。

Architeture:

type T_STATE is (ST_IDLE, ST_WORKING);

signal State      : T_STATE   := ST_IDLE;
signal NextState  : T_STATE;

体:

process(Clock)
begin
  if rising_edge(Clock) then
    if (Reset = '1') then
      State <= ST_IDLE;
    else
      State <= NextState;
    end if;
  end if;
end process;

process(State, Input)
begin
  NextState    <= State;

  -- default assignments
  Output       <= '0';

  case State is
    when ST_IDLE =>
      if (Input = '1') then
        NextState  <= ST_WORKING;
      end if;

    when ST_WORKING =>
      Output       <= '1';
      NextState    <= ST_IDLE;

  end case;
end process;