Question

我正在学习VHDL而且我已经停止了。我想用更小的门（这里是一个与非门）创建一个简单的门。这是代码：

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity ANDGATE2 is
     port(
         x,y  : in STD_LOGIC;
         z    : out STD_LOGIC
         );
end ANDGATE2;

architecture ANDGATE2 of ANDGATE2 is
begin

    z <= x AND y;

end ANDGATE2;

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity NOTGATE1 is
     port(
         x : in STD_LOGIC;
         z : out STD_LOGIC
         );
end NOTGATE1;

architecture NOTGATE1 of NOTGATE1 is
begin

    z <= NOT x;

end NOTGATE1;       

library  ieee;
use  ieee.std_logic_1164.all;

entity NANDGATE2 is
     port(
         x : in STD_LOGIC;
         y : in STD_LOGIC;
         z : out STD_LOGIC
         );
end NANDGATE2;

architecture NANDGATE2 of NANDGATE2 is   
signal c, d: std_logic;
    component NOTGATE1
         port(
             n_in : in STD_LOGIC;
             n_out : out STD_LOGIC
             );
    end component;  
    component ANDGATE2
        port(
             a_in1, a_in2 : in STD_LOGIC;
             a_out        : out STD_LOGIC
             );
    end component;
begin     
    N0: ANDGATE2
    port map(x, y, c);
    N1: NOTGATE1
    port map(c, d); 

    z <= d;

end NANDGATE2;

这是我作为模板使用的一些教程中的代码;它编译没有任何问题。

library  ieee;
use  ieee.std_logic_1164.all;

-- definition of a full adder

entity FULLADDER is
    port 
    (
        a, b, c: in std_logic;
        sum, carry: out std_logic
    );
end FULLADDER;     

architecture fulladder_behav of FULLADDER is
begin
sum <= (a xor b) xor c ;
carry <= (a and b) or (c and (a xor b));
     end fulladder_behav;

     -- 4-bit adder

library  ieee;
use  ieee.std_logic_1164.all;

entity FOURBITADD is
    port 
    (
        a, b: in std_logic_vector(3 downto 0);
        Cin : in std_logic;
        sum: out std_logic_vector (3 downto 0);
        Cout, V: out std_logic
    );
end FOURBITADD;

architecture fouradder_structure of FOURBITADD is
     signal c: std_logic_vector (4 downto 0);
component FULLADDER
    port
    (
        a, b, c: in std_logic;
        sum, carry: out std_logic
    );
end component;

begin
           FA0: FULLADDER
                port map (a(0), b(0), Cin, sum(0), c(1));
           FA1: FULLADDER
                port map (a(1), b(1), C(1), sum(1), c(2));
           FA2: FULLADDER
                port map (a(2), b(2), C(2), sum(2), c(3));
           FA3: FULLADDER
                port map (a(3), b(3), C(3), sum(3), c(4));
           V <= c(3) xor c(4);
           Cout <= c(4);
end fouradder_structure;

我的代码编译没有错误，但有两个警告：

# Warning: ELAB1_0026: p2.vhd : (85, 0): There is no default binding for component "andgate2".(Port "a_in1" is not on the entity).
# Warning: ELAB1_0026: p2.vhd : (87, 0): There is no default binding for component "notgate1".(Port "n_in" is not on the entity).

是什么给出了？

Answer 1

您需要在组件和实体声明中使用相同的端口名称。

现在，例如在您的NOTGATE1实体声明中，您有输入端口x和输出端口z，但在NANDGATE2体系结构中，您声明{ {1}}组件包含端口NOTGATE1和n_in。

这不会在编译期间引起问题，因为编译一次只查看一个单元，并且不会看到实际的实体。在精化阶段，您的工具将尝试将实体与组件匹配，但由于端口不匹配，这将失败。

Answer 2

不是100％肯定，但我认为component声明中的引脚需要与entity块中的引脚匹配：

component NOTGATE1
     port(
         x : in STD_LOGIC;
         z : out STD_LOGIC
         );
end component;  
component ANDGATE2
    port(
         x,y : in STD_LOGIC;
         z   : out STD_LOGIC
         );

Answer 3

始终在端口映射中使用显式端口绑定，例如

port map(a_in1 => x, 
         a_in2 => y, 
         a_out => c);

它会使您的代码更加清晰。在大型项目中，这是第一个经验法则。

VHDL门基础知识

3 个答案: