我正在尝试实现一个交通信号灯控制器。将有3条道路，每条道路都会有一个交通信号灯控制器。我正在使用basy3板上已经存在的时钟。是100MHz我尝试在绿色上等待5秒钟，当它变成黄色时，将需要1秒钟，因此我创建了一个常数来计数5或1秒。这是我的代码，当我将basys3连接到面包板以查看输出时，在大多数状态下，始终黄色指示灯点亮为绿色或红色指示灯点亮，但它应该单独点亮。我可以使用等待语句来防止此问题吗？
这是我的代码：
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
entity traffic_lights is
port(
clk : in STD_LOGIC;
-- red1 represents red light of 1st traffic light
-- similarily other lights are represented
clk_reset: in STD_LOGIC;
red1 : out STD_LOGIC;
yellow1 : out STD_LOGIC;
green1 : out STD_LOGIC;
red2 : out STD_LOGIC;
yellow2 : out STD_LOGIC;
green2 : out STD_LOGIC;
red3 : out STD_LOGIC;
yellow3 : out STD_LOGIC;
green3 : out STD_LOGIC
);
end entity traffic_lights;
architecture Behavioral of traffic_lights is
type state_type is (s0, s1, s2, s3, s4, s5,s6,s7,s8,s9,s10,s11); -- defined state for each combination possible
signal state : state_type := s0; -- initial state is s0
signal count : integer := 0; -- represents time
constant one_second: integer:= 100000000;
signal lights: std_logic_vector(8 downto 0); -- a vector that represents a state
begin
process(clk, clk_reset)
begin
if clk_reset = '1' then
state <= s0;
count <= 0;
elsif clk'event and clk = '1' then
case state is
when s0 =>
if count < one_second then
state <= s0;
count <= count + 1;
else
state <= s1;
count <= 0;
end if;
when s1 =>
if count < one_second then
state <= s1;
count <= count + 1;
else
state <= s2;
count <= 0;
end if;
when s2 =>
if count < one_second*5 then
state <= s2;
count <= count + 1;
else
state <= s3;
count <= 0;
end if;
when s3 =>
if count < one_second then
state <= s3;
count <= count + 1;
else
state <= s4;
count <= 0;
end if;
when s4 =>
if count < one_second then
state <= s4;
count <= count + 1;
else
state <= s5;
count <= 0;
end if;
when s5 =>
if count < one_second then
state <= s5;
count <= count + 1;
else
state <= s6;
count <= 0;
end if;
when s6 =>
if count < one_second*5 then
state <= s6;
count <= count + 1;
else
state <= s7;
count <= 0;
end if;
when s7 =>
if count < one_second then
state <= s7;
count <= count + 1;
else
state <= s8;
count <= 0;
end if;
when s8 =>
if count < one_second then
state <= s8;
count <= count + 1;
else
state <= s9;
count <= 0;
end if;
when s9 =>
if count < one_second then
state <= s9;
count <= count + 1;
else
state <= s10;
count <= 0;
end if;
when s10 =>
if count < one_second*5 then
state <= s10;
count <= count + 1;
else
state <= s11;
count <= count + 1;
end if;
when s11 =>
if count < one_second then
state <= s11;
count <= count + 1;
else
state <= s0;
count <= 0;
end if;
when others =>
state <= s0;
end case;
end if;
end process;
C2: process(state)
begin
case state is
when s0 => lights <= "100100100";
when s1 => lights <= "010100100";
when s2 => lights <= "001100100";
when s3 => lights <= "010100100";
when s4 => lights <= "100100100";
when s5 => lights <= "100010100";
when s6 => lights <= "100001100";
when s7 => lights <= "100010100";
when s8 => lights <= "100100100";
when s9 => lights <= "100100010";
when s10 => lights <= "100100001";
when s11 => lights <= "100100010";
when others => lights <= "100100100";
end case;
end process;
red1 <= lights(0);
yellow1 <= lights(1);
green1 <= lights(2);
red2 <= lights(3);
yellow2 <= lights(4);
green2 <= lights(5);
red3 <= lights(6);
yellow3 <= lights(7);
green3 <= lights(8);
end architecture Behavioral;
以下是约束：
## Clock signal
set_property PACKAGE_PIN W5 [get_ports {clk}]
set_property IOSTANDARD LVCMOS33 [get_ports {clk}]
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk}]
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets enable_IBUF]
##Buttons
set_property PACKAGE_PIN U18 [get_ports clk_reset]
set_property IOSTANDARD LVCMOS33 [get_ports clk_reset]
#set_property PACKAGE_PIN T18 [get_ports {up_enable}]
# set_property IOSTANDARD LVCMOS33 [get_ports {up_enable}]
##set_property PACKAGE_PIN W19 [get_ports {enable}]
# #set_property IOSTANDARD LVCMOS33 [get_ports {enable}]
##set_property PACKAGE_PIN T17 [get_ports btnR]
# #set_property IOSTANDARD LVCMOS33 [get_ports btnR]
#set_property PACKAGE_PIN U17 [get_ports {down_enable}]
# set_property IOSTANDARD LVCMOS33 [get_ports {down_enable}]
##Pmod Header JB
##Sch name = JB1
set_property PACKAGE_PIN A14 [get_ports {red1}]
set_property IOSTANDARD LVCMOS33 [get_ports {red1}]
#Sch name = JB2
set_property PACKAGE_PIN A16 [get_ports {yellow1}]
set_property IOSTANDARD LVCMOS33 [get_ports {yellow1}]
#Sch name = JB3
set_property PACKAGE_PIN B15 [get_ports {green1}]
set_property IOSTANDARD LVCMOS33 [get_ports {green1}]
#Sch name = JB4
set_property PACKAGE_PIN B16 [get_ports {red2}]
set_property IOSTANDARD LVCMOS33 [get_ports {red2}]
#Sch name = JB7
set_property PACKAGE_PIN A15 [get_ports {yellow2}]
set_property IOSTANDARD LVCMOS33 [get_ports {yellow2}]
#Sch name = JB8
set_property PACKAGE_PIN A17 [get_ports {green2}]
set_property IOSTANDARD LVCMOS33 [get_ports {green2}]
##Sch name = JB9
#set_property PACKAGE_PIN C15 [get_ports {JB[6]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {JB[6]}]
##Sch name = JB10
#set_property PACKAGE_PIN C16 [get_ports {JB[7]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {JB[7]}]
##Pmod Header JC
##Sch name = JC1
set_property PACKAGE_PIN K17 [get_ports {red3}]
set_property IOSTANDARD LVCMOS33 [get_ports {red3}]
#Sch name = JC2
set_property PACKAGE_PIN M18 [get_ports {yellow3}]
set_property IOSTANDARD LVCMOS33 [get_ports {yellow3}]
#Sch name = JC3
set_property PACKAGE_PIN N17 [get_ports {green3}]
set_property IOSTANDARD LVCMOS33 [get_ports {green3}]
##Sch name = JC4
#set_property PACKAGE_PIN P18 [get_ports {lights[3]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {lights[3]}]
##Sch name = JC7
#set_property PACKAGE_PIN L17 [get_ports {lights[4]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {lights[4]}]
##Sch name = JC8
#set_property PACKAGE_PIN M19 [get_ports {lights[5]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {lights[5]}]
##Sch name = JC9
#set_property PACKAGE_PIN P17 [get_ports {JC[6]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}]
##Sch name = JC10
#set_property PACKAGE_PIN R18 [get_ports {JC[7]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}]