VHDL无法初始化无符号向量数组

Question

行：

type some_array_type is array (0 to 4, 0 to 4) of unsigned(7 downto 0);
signal some_array : some_array_type := (others=>(others=>'0')); 

导致vivado 2018.2引发错误：

[Synth 8-1807] character '0' is not in type unresolved_unsigned

由于某种原因在VHDL 2008文件中。使Vivado意识到我只是试图将数组初始化为零，这是什么神奇的语法？我不必编写一个函数来执行此操作。我也尝试了unsigned（（others =>（others =>'0'）））;

下面的代码当然可以忽略，并且根本不需要任何代码。对于强迫症患者来说，它就在那里。 “您必须始终包含一个最小的工作示例！”

library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.numeric_std.all;

entity some_entity is
    port (
        clk, rst: in std_logic ;
    );
end some_entity ;

architecture arch of some_entity is
    type some_array_type is array (0 to 4, 0 to 4) of unsigned(7 downto 0);
    -- throws error
    signal some_array : some_array_type := (others=>(others=>'0'));

    type some_other_array_type is array (natural range <>) of std_logic_vector(7 downto 0); 
    -- doesn't throw error
    signal some_other_array : some_other_array_type(0 to 4) := (others=>(others=>'0'));
begin
    -- some made up process
    process(clk, rst)
        begin
            if(rising_edge(clk)) then
                if rst = '1' then
                    some_array <= (others=>(others=>'0'));
                else
                    some_array <= (others=>(others=>'1'));
                end if;
            end if;
    end process;
end arch;