Question

有没有人知道如何在向量数组中输入或强制？我相信它就是这样，但它不起作用。

--------- Test Bench ---------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use work.mypackage2.all;

ENTITY test_bench IS
PORT (H   : in  enter_vector := ("1100","0011","1111","1101","1100","0011","1111","1101","1100","0011","1111","1101","1100","0011","1111","1101");
      L   : in  enter_vector := ("1100","0011","1111","1101","1100","0011","1111","1101","1100","0011","1111","1101","1100","0011","1111","1101");
        X   : out integer);
END entity;
ARCHITECTURE comportamento OF test_bench IS



COMPONENT MUX is
    Port ( SEL : in  STD_LOGIC;
           H   : in  enter_vector;
           L   : in  enter_vector;
           X   : out enter_vector;
              Sinal: out std_logic -- it is 1 if H and 0 if L
              );
END COMPONENT;


COMPONENT choose is
    Port ( SEL : in  STD_LOGIC;
           E   : in  enter_vector;
           X    : out integer);
END COMPONENT;

signal VC : enter_vector;
signal sin,sel: std_logic; 



BEGIN

m:  MUX PORT MAP (sel,H,L,VC,sin);
cc: choose PORT MAP (sin,VC,X);




END comportamento;

------- Type Created-----

    library IEEE; 
    use IEEE.STD_LOGIC_1164.all; 

    package mypackage2 is 

              type enter_vector is array (15 to 0) of std_logic_vector(3 downto 0); -- array of bytes 

    end mypackage2; 


    package body mypackage2 is 

    end mypackage2;

Answer 1

而不是：

type enter_vector is array (15 to 0) of std_logic_vector(3 downto 0);
--                              ^
--                              |

你需要这个：

type enter_vector is array (15 downto 0) of std_logic_vector(3 downto 0);
--                                ^
--                                |

这是一个讨厌的＆＃34;陷阱＆＃34;在VHDL中。使用to代替downto并不是错误，但最终会得到一个长度为0的数组。这通常会导致代码中其他地方出现其他错误。

如何强制输入和向量数组

1 个答案: