减去数组的所有元素:VHDL

时间:2018-10-19 14:13:22

标签: vhdl

我正在接收数据。为了存储,我声明了一个数组:

type fifo_array is array(0 to 66) of std_logic_vector(7 downto 0);
signal ins_fifo_array: fifo_array := (others => (others => '0'));

在此过程中,将填充不同的字(字节)。我想从此数组的所有元素中减去x30(hex)的偏移量,并将其分配给另一个数组以进行进一步处理。显然像这样初始化它:

type fifo_second_array is array(0 to 66) of std_logic_vector(7 downto 0);
signal ins_fifo_second_array: fifo_second_array := (ins_fifo_array - x"30"); 

不起作用。还有另一种解决方案,例如:

type fifo_second_array is array(0 to 66) of std_logic_vector(7 downto 0);
signal ins_fifo_second_array: fifo_second_array := (ins_fifo_array(0) - x"30",....);

这也不起作用。请提出建议。

1 个答案:

答案 0 :(得分:0)

process(ins_fifo_array)
  variable I     : natural;
  constant C_x30 : unsigned := x"30";
begin 

  for I in 0 to 66 loop
    ins_fifo_second_array(I) <= std_logic_vector(unsigned(ins_fifo_array(I)) - C_x30);
  end loop;

end process;