Question

我想要做的如下：

我正在使用数组的几个元素，将它们与固定值进行比较，然后尝试从中创建向量。

这是一段代码：

architecture behav of main_ent is
... 
type f_array is array(0 to 8) of std_logic_vector(7 downto 0);
signal ins_f_array: f_array;
signal sel_sig_cmd : std_logic_vector(3 downto 0); 
...
process begin
sel_sig_cmd <= ((ins_f_array(4) = x"3A")&(ins_f_array(3)= x"3A")&(ins_f_array(2)= x"3A")&(ins_f_array(1)= x"3A"));

....
end process;
...

该参数应为 sel_sig_cmd = 1000 ，或者为 1011等。但这是行不通的。此代码还有其他选择吗？

干杯

Tahir

Answer 1

这是因为VHDL中的=函数返回一个布尔值，而不是std_logic。在VHDL '93中，除了手动设置每个位，没有其他整齐的方法可以做到这一点：

sel_sig_cmd(3) <= '1' when (ins_f_array(4) = x"3A") else '0'
sel_sig_cmd(2) <= '1' when (ins_f_array(3) = x"3A") else '0'
-- etc

但是在VHDL 2008中，存在关系运算符（？=？/ =等），它们在比较时返回std_logic。因此您的代码变为：

sel_sig_cmd <= (   (ins_f_array(4) ?= x"3A")
                 & (ins_f_array(3) ?= x"3A")
                 & (ins_f_array(2) ?= x"3A")
                 & (ins_f_array(1) ?= x"3A") );

Answer 2

Tricky的答案很不错。但是，如果要在流程中实现它，则可以按以下方式重写该流程：

architecture behav of main_ent is
... 
type f_array is array(0 to 8) of std_logic_vector(7 downto 0);
signal ins_f_array: f_array;
signal sel_sig_cmd : std_logic_vector(3 downto 0); 
...
process(ins_f_array(4 downto 1)) begin
if ((ins_f_array(4) = x"3A")&(ins_f_array(3)= x"3A")&
              (ins_f_array(2)= x"3A")&(ins_f_array(1)= x"3A")) then
sel_sig_cmd <= "XXXX" -- Enter your desired value
....
end process;
...

此过程将很繁琐，因为它必须涵盖“ if条件”的所有16种可能性。

另一种实现方式是对每个位使用if条件，如下所示：

architecture behav of main_ent is
... 
type f_array is array(0 to 8) of std_logic_vector(7 downto 0);
signal ins_f_array: f_array;
signal sel_sig_cmd : std_logic_vector(3 downto 0); 
...
process(ins_f_array(4 downto 1)) begin
if (ins_f_array(4) = x"3A") then
sel_sig_cmd(3) <= "X" -- Enter your desired value
else
sel_sig_cmd(3) <= "X" -- Enter your desired value
end if;
-- Repeat for other bits
....
end process;
...

Answer 3

您可以重载“ =”运算符：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity tb is
end entity;

architecture behav of tb is

  function "=" (Left, Right: std_logic_vector) return std_logic is
  begin
    if (Left = Right) then
      return '1';
    else
      return '0';
    end if;
  end function "=";


  type f_array is array(0 to 8) of std_logic_vector(7 downto 0);
  signal ins_f_array: f_array := (x"00",x"01",x"02",x"03",x"04",x"05",x"06",x"07",x"08");
  signal sel_sig_cmd : std_logic_vector(3 downto 0); 

  begin

    process (ins_f_array(1 to 4)) begin
      sel_sig_cmd <= ((ins_f_array(4) = x"3A")&(ins_f_array(3) = x"3A")&(ins_f_array(2) = x"3A")&(ins_f_array(1) = x"3A"));
    end process;

    process
    begin
      wait for 10 us;
      for i in 0 to 8 loop  
        ins_f_array(i) <= std_logic_vector(unsigned(ins_f_array(i)) + 1);
      end loop;
    end process;

end architecture;

VHDL中的串联运算符：比较数组的元素并生成向量

3 个答案: