我是使用vivado工具的新功能，并且我正在尝试做乘数。
，即时通讯不使用时钟作为乘法器。只是逻辑电路。
而且我有传播延迟的问题。
您能告诉我我如何看待传播延迟吗？还是没有任何工具可以查看vivado中的传播延迟，该如何测量延迟？
这是我的代码
`timescale 1ns / 1ns
module full_adder(A, B, C_in, C_out, S );
input A,B,C_in;
output S,C_out;
wire line1;
wire line2;
wire line3;
wire line4;
wire line5;
assign line1 = A^B,
line2 = line1 ^ C_in,
line3 = line1 & C_in,
line4 = A & B,
line5 = line3 | line4;
assign S = line2;
assign C_out = line5;
endmodule
`timescale 1ns / 1ns
module three_input_FA(a,b,v,h,
s_in,
s_out, c_in, c_out );
input a, b, v, h, s_in, c_in;
output s_out, c_out;
wire vh;
wire vhab;
assign vh = v ^ h;
assign vhab = vh & a & b;
full_adder inst1(s_in, vhab, c_in, c_out, s_out);
endmodule
`timescale 1ns / 1ps
module useful_2by2(
a,b,v,h,s_in,s_out,c_in,c_out
);
input [1:0] a;
input [1:0] b;
input [1:0] v;
input [1:0] h;
output [2:0] s_in;
output [2:0] s_out;
output [1:0] c_in;
output [1:0] c_out;
wire [2:0]s0_in;
wire [3:0]s0_out;
wire [1:0]c0_in;
wire [3:0]c0_out;
three_input_FA inst1(a[0],b[0], v[0],h[0], s0_in[0], s0_out[0], c0_in[0], c0_out[0]); //inst1의 c_out1이 inst2의 c_in 부분으로 연결
three_input_FA inst2(a[1],b[0], v[1],h[0], s0_in[1], s0_out[1], c0_out[0], c0_out[1]);
three_input_FA inst3(a[0],b[1], v[0],h[1], s0_out[1],s0_out[2], c0_in[1], c0_out[2]);
three_input_FA inst4(a[1],b[1], v[1],h[1], s0_in[2], s0_out[3], c0_out[2], c0_out[3]);
assign c_out[0] = c0_out[1], c_out[1] = c0_out[3];
assign s_out[0] = s0_out[0], s_out[1] = s0_out[2], s_out[2] = s0_out[3];
assign c0_in[0] = c_in[0] , c0_in[1] = c_in[1];
assign s0_in[0] = s_in[0], s0_in[1] = s_in[1], s0_in[2] = s_in[2];
endmodule
`timescale 1ns / 1ps
module useful_4by4(
a,b,v,h,s_in,s_out,c_in,c_out
);
input [3:0]a;
input [3:0]b;
input [3:0] v;
input [3:0] h;
output [6:0]s_in;
output [6:0]s_out;
output [3:0]c_in;
output [3:0]c_out;
wire [11:0] s0_in;
wire [11:0] s0_out;
wire [7:0] c0_in;
wire [7:0] c0_out;
useful_2by2 inst1(a[1:0],b[1:0], v[1:0], h[1:0], s0_in[2:0], s0_out[2:0], c0_in[1:0], c0_out[1:0]);
useful_2by2 inst2(a[3:2],b[1:0], v[3:2], h[1:0], s0_in[5:3], s0_out[5:3], c0_in[3:2], c0_out[3:2]);
useful_2by2 inst3(a[1:0],b[3:2], v[1:0], h[3:2], s0_in[8:6], s0_out[8:6], c0_in[5:4], c0_out[5:4]);
useful_2by2 inst4(a[3:2],b[3:2], v[3:2], h[3:2], s0_in[11:9], s0_out[11:9], c0_in[7:6], c0_out[7:6]);
assign c0_in[2] = c0_out[0], c0_in[3] = c0_out[1],
c0_in[6] = c0_out[4], c0_in[7] = c0_out[5];
assign s0_in[6] = s0_out[2], s0_in[7] = s0_out[4],
s0_in[9] = s0_out[5],
s0_in[2] = s0_out[3], s0_in[8] = s0_out[9];
assign c_out[0] = c0_out[2], c_out[1] = c0_out[3], c_out[2] = c0_out[6], c_out[3] = c0_out[7];
assign s0_in[0] = s_in[0], s0_in[1] = s_in[1], s0_in[3] = s_in[2], s0_in[4] = s_in[3],
s0_in[5] = s_in[4], s0_in[10] = s_in[5], s0_in[11] = s_in[6];
assign c0_in[0] = c_in[0], c0_in[1] = c_in[1], c0_in[4] = c_in[2], c0_in[5] = c_in[3];
assign s_out[0] = s0_out[0], s_out[1] = s0_out[1], s_out[2] = s0_out[6], s_out[3] = s0_out[7],
s_out[4] = s0_out[8], s_out[5] = s0_out[10], s_out[6] = s0_out[11];
//s_in to c_out link
/*assign s_in[4] = c_out[0], s_in[5] = c_out[1], s_in[6] = c_out[2];*/
endmodule
`timescale 1ns / 1ps
module useful_8by8(
a,b,v,h,s_in,s_out,c_in,c_out
);
input [7:0]a;
input [7:0]b;
input [7:0] v;
input [7:0] h;
output [14:0]s_in;
output [14:0]s_out;
output [7:0]c_in;
output [7:0]c_out;
wire [27:0]s0_in;
wire [27:0]s0_out;
wire [15:0]c0_in;
wire [15:0]c0_out;
useful_4by4 inst1(a[3:0], b[3:0], v[3:0], h[3:0], s0_in[6:0], s0_out[6:0], c0_in[3:0], c0_out[3:0]);
useful_4by4 inst2(a[7:4], b[3:0], v[7:4], h[3:0], s0_in[13:7], s0_out[13:7], c0_in[7:4], c0_out[7:4]);
useful_4by4 inst3(a[3:0], b[7:4], v[3:0], h[7:4], s0_in[20:14], s0_out[20:14], c0_in[11:8], c0_out[11:8]);
useful_4by4 inst4(a[7:4], b[7:4], v[7:4], h[7:4], s0_in[27:21], s0_out[27:21], c0_in[15:12], c0_out[15:12]);
assign c0_in[4] = c0_out[0], c0_in[5] = c0_out[1], c0_in[6] = c0_out[2], c0_in[7] = c0_out[3],
c0_in[12] = c0_out[8], c0_in[13] = c0_out[9], c0_in[14] = c0_out[10], c0_in[15] = c0_out[11];
assign s0_in[14] = s0_out[4], s0_in[15] = s0_out[5], s0_in[16] = s0_out[6], s0_in[17] = s0_out[10],
s0_in[21] = s0_out[11], s0_in[22] = s0_out[12], s0_in[23] = s0_out[13],
s0_in[4] = s0_out[7], s0_in[5] = s0_out[8], s0_in[6] = s0_out[9], s0_in[18] = s0_out[21],
s0_in[19] = s0_out[22], s0_in[20] = s0_out[23];
//output
assign c_out[0] = c0_out[4], c_out[1] = c0_out[5], c_out[2] = c0_out[6], c_out[3] = c0_out[7],
c_out[4] = c0_out[12], c_out[5] = c0_out[13], c_out[6] = c0_out[14], c_out[7] = c0_out[15];
assign s0_in[0] = s_in[0], s0_in[1] = s_in[1], s0_in[2] = s_in[2], s0_in[3] = s_in[3],
s0_in[7] = s_in[4], s0_in[8] = s_in[5], s0_in[9] = s_in[6], s0_in[10] = s_in[7],
s0_in[11] = s_in[8], s0_in[12] = s_in[9], s0_in[13] = s_in[10], s0_in[24] = s_in[11],
s0_in[25] = s_in[12], s0_in[26] = s_in[13], s0_in[27] = s_in[14];
assign c0_in[0] = c_in[0], c0_in[1] = c_in[1], c0_in[2] = c_in[2], c0_in[3] = c_in[3],
c0_in[8] = c_in[4], c0_in[9] = c_in[5], c0_in[10] = c_in[6],c0_in[11] = c_in[7];
assign s_out[0] = s0_out[0], s_out[1] = s0_out[1], s_out[2] = s0_out[2], s_out[3] = s0_out[3],
s_out[4] = s0_out[14], s_out[5] = s0_out[15], s_out[6] = s0_out[16], s_out[7] = s0_out[17],
s_out[8] = s0_out[18], s_out[9] = s0_out[19], s_out[10] = s0_out[20], s_out[11] = s0_out[24],
s_out[12] = s0_out[25], s_out[13] = s0_out[26], s_out[14] = s0_out[27];
// c_out to s_in link
/*assign s_in[8] = c_out[0], s_in[9] = c_out[1], s_in[10] = c_out[2], s_in[11] = c_out[3],
s_in[12] = c_out[4], s_in[13] = c_out[5], s_in[14] = c_out[6];*/
endmodule
`timescale 1ns / 1ps
module module_16by16(
a,b,v,h,s_in,s_out,c_in,c_out
);
input [15:0]a;
input [15:0]b;
input [15:0] v;
input [15:0] h;
output [30:0]s_in;
output [30:0]s_out;
output [15:0]c_in;
output [15:0]c_out;
wire [59:0]s0_in;
wire [59:0]s0_out;
wire [31:0]c0_in;
wire [31:0]c0_out;
useful_8by8 inst1(a[7:0], b[7:0], v[7:0], h[7:0], s0_in[14:0], s0_out[14:0], c0_in[7:0], c0_out[7:0]);
useful_8by8 inst2(a[15:8],b[7:0], v[15:8], h[7:0], s0_in[29:15], s0_out[29:15], c0_in[15:8], c0_out[15:8]);
useful_8by8 inst3(a[7:0], b[15:8], v[7:0], h[15:8], s0_in[44:30], s0_out[44:30], c0_in[23:16], c0_out[23:16]);
useful_8by8 inst4(a[15:8],b[15:8], v[15:8], h[15:8], s0_in[59:45], s0_out[59:45], c0_in[31:24], c0_out[31:24]);
assign c0_in[8] = c0_out[0], c0_in[9] = c0_out[1], c0_in[10] = c0_out[2], c0_in[11] = c0_out[3],
c0_in[12] = c0_out[4], c0_in[13] = c0_out[5], c0_in[14] = c0_out[6], c0_in[15] = c0_out[7],
c0_in[24] = c0_out[16], c0_in[25] = c0_out[17], c0_in[26] = c0_out[18], c0_in[27] = c0_out[19],
c0_in[28] = c0_out[20], c0_in[29] = c0_out[21], c0_in[30] = c0_out[22], c0_in[31] = c0_out[23];
assign s0_in[30] = s0_out[8], s0_in[31] = s0_out[9], s0_in[32] = s0_out[10], s0_in[33] = s0_out[11],
s0_in[34] = s0_out[12], s0_in[35] = s0_out[13], s0_in[36] = s0_out[14], s0_in[37] = s0_out[22],
s0_in[45] = s0_out[23], s0_in[46] = s0_out[24], s0_in[47] = s0_out[25], s0_in[48] = s0_out[26],
s0_in[49] = s0_out[27], s0_in[50] = s0_out[28], s0_in[51] = s0_out[29],
s0_in[8] = s0_out[15], s0_in[9] = s0_out[16], s0_in[10] = s0_out[17], s0_in[11] = s0_out[18],
s0_in[12] = s0_out[19], s0_in[13] = s0_out[20], s0_in[14] = s0_out[21],
s0_in[38] = s0_out[45], s0_in[39] = s0_out[46], s0_in[40] = s0_out[47], s0_in[41] = s0_out[48],
s0_in[42] = s0_out[49], s0_in[43] = s0_out[50], s0_in[44] = s0_out[51];
//output
assign c0_in[0] = c_in[0], c0_in[1] = c_in[1], c0_in[2] = c_in[2], c0_in[3] = c_in[3],
c0_in[4] = c_in[4], c0_in[5] = c_in[5], c0_in[6] = c_in[6], c0_in[7] = c_in[7],
c0_in[16] = c_in[8], c0_in[17] = c_in[9], c0_in[18] = c_in[10], c0_in[19] = c_in[11],
c0_in[20] = c_in[12], c0_in[21] = c_in[13], c0_in[22] = c_in[14], c0_in[23] = c_in[15];
assign c_out[0] = c0_out[8], c_out[1] = c0_out[9], c_out[2] = c0_out[10], c_out[3] = c0_out[11],
c_out[4] = c0_out[12], c_out[5] = c0_out[13], c_out[6] = c0_out[14], c_out[7] = c0_out[15],
c_out[8] = c0_out[24], c_out[9] = c0_out[25], c_out[10] = c0_out[26], c_out[11] = c0_out[27],
c_out[12] = c0_out[28], c_out[13] = c0_out[29], c_out[14] = c0_out[30], c_out[15] = c0_out[31];
assign s0_in[0] = s_in[0], s0_in[1] = s_in[1], s0_in[2] = s_in[2], s0_in[3] = s_in[3], s0_in[4] = s_in[4], s0_in[5] = s_in[5],
s0_in[6] = s_in[6], s0_in[7] = s_in[7], s0_in[15] = s_in[8], s0_in[16] = s_in[9], s0_in[17] = s_in[10],s0_in[18] = s_in[11],
s0_in[19] = s_in[12],s0_in[20] = s_in[13],s0_in[21] = s_in[14],s0_in[22] = s_in[15],s0_in[23] = s_in[16],s0_in[24] = s_in[17],
s0_in[25] = s_in[18],s0_in[26] = s_in[19],s0_in[27] = s_in[20],s0_in[28] = s_in[21],s0_in[29] = s_in[22],s0_in[52] = s_in[23],
s0_in[53] = s_in[24],s0_in[54] = s_in[25],s0_in[55] = s_in[26],s0_in[56] = s_in[27],s0_in[57] = s_in[28],s0_in[58] = s_in[29],
s0_in[59] = s_in[30];
assign s_out[0] = s0_out[0], s_out[1] = s0_out[1], s_out[2] = s0_out[2], s_out[3] = s0_out[3], s_out[4] = s0_out[4], s_out[5] = s0_out[5],
s_out[6] = s0_out[6], s_out[7] = s0_out[7], s_out[8] = s0_out[30], s_out[9] = s0_out[31], s_out[10] = s0_out[32], s_out[11] = s0_out[33],
s_out[12] = s0_out[34], s_out[13] = s0_out[35], s_out[14] = s0_out[36], s_out[15] = s0_out[37], s_out[16] = s0_out[38], s_out[17] = s0_out[39],
s_out[18] = s0_out[40], s_out[19] = s0_out[41], s_out[20] = s0_out[42], s_out[21] = s0_out[43], s_out[22] = s0_out[44], s_out[23] = s0_out[52],
s_out[24] = s0_out[53], s_out[25] = s0_out[54], s_out[26] = s0_out[55], s_out[27] = s0_out[56], s_out[28] = s0_out[57], s_out[29] = s0_out[58],
s_out[30] = s0_out[59];
//c_out link to s_in
assign s_in[16] = c_out[0], s_in[17] = c_out[1], s_in[18] = c_out[2], s_in[19] = c_out[3],
s_in[20] = c_out[4], s_in[21] = c_out[5], s_in[22] = c_out[6], s_in[23] = c_out[7],
s_in[24] = c_out[8], s_in[25] = c_out[9], s_in[26] = c_out[10], s_in[27] = c_out[11],
s_in[28] = c_out[12], s_in[29] = c_out[13], s_in[30] = c_out[14];
endmodule
`timescale 1ns / 1ps
module top_16by16(
a,b,v,h,p
);
input [15:0] a;
input [15:0] b;
input [15:0] v;
input [15:0] h;
output [31:0]p;
wire [30:0]s_in;
wire [30:0]s_out;
wire [15:0]c_in;
wire [15:0]c_out;
module_16by16 inst1(a,b,v,h,s_in,s_out,c_in,c_out);
assign s_in[0] = 0, s_in[1] = 0, s_in[2] = 0, s_in[3] = 0, s_in[4] = 0, s_in[5] = 0, s_in[6] = 0, s_in[7] = 0,
s_in[8] = 0, s_in[9] = 0, s_in[10] = 0, s_in[11] = 0, s_in[12] = 0, s_in[13] = 0, s_in[14] = 0, s_in[15] = 0;
assign c_in[0] = 0, c_in[1] = 0, c_in[2] = 0, c_in[3] = 0, c_in[4] = 0, c_in[5] = 0, c_in[6] = 0, c_in[7] = 0,
c_in[8] = 0, c_in[9] = 0, c_in[10] = 0, c_in[11] = 0, c_in[12] = 0, c_in[13] = 0, c_in[14] = 0, c_in[15] = 0;
assign p[0] = s_out[0], p[1] = s_out[1], p[2] = s_out[2], p[3] = s_out[3],
p[4] = s_out[4], p[5] = s_out[5], p[6] = s_out[6], p[7] = s_out[7],
p[8] = s_out[8], p[9] = s_out[9], p[10] = s_out[10], p[11] = s_out[11],
p[12] = s_out[12], p[13] = s_out[13], p[14] = s_out[14], p[15] = s_out[15],
p[16] = s_out[16], p[17] = s_out[17], p[18] = s_out[18], p[19] = s_out[19],
p[20] = s_out[20], p[21] = s_out[21], p[22] = s_out[22], p[23] = s_out[23],
p[24] = s_out[24], p[25] = s_out[25], p[26] = s_out[26], p[27] = s_out[27],
p[28] = s_out[28], p[29] = s_out[29], p[30] = s_out[30], p[31] = c_out[15];
endmodule
`timescale 1ns / 1ps
module test_16by16();
reg [15:0] a;
reg [15:0] b;
reg [15:0] v;
reg [15:0] h;
wire [31:0] p;
integer i0,i1,i2,i3,i4,i5,i6,i7,i8,i9,i10,i11,i12,i13,i14,i15,
j0,j1,j2,j3,j4,j5,j6,j7,j8,j9,j10,j11,j12,j13,j14,j15;
top_16by16 test(
.a(a),.b(b),
.v(v),.h(h),
.p(p)
);
initial begin
a[15:0] = 1'b0;
b[15:0] = 1'b0;
v[0] = 0; h[0] = 1; v[4] = 0; h[4] = 1;
v[1] = 0; h[1] = 1; v[5] = 0; h[5] = 1;
v[2] = 0; h[2] = 1; v[6] = 0; h[6] = 1;
v[3] = 0; h[3] = 1; v[7] = 0; h[7] = 1;
v[8] = 0; h[8] = 1; v[12] = 0; h[12] = 1;
v[9] = 0; h[9] = 1; v[13] = 0; h[13] = 1;
v[10] = 0; h[10] = 1; v[14] = 0; h[14] = 1;
v[11] = 0; h[11] = 1; v[15] = 0; h[15] = 1;
for(i0=0;i0<2;i0=i0+1) //a15
begin
for(i1=0;i1<2;i1=i1+1) //a14
begin
for(i2=0;i2<2;i2=i2+1) //a13
begin
for(i3=0;i3<2;i3=i3+1) //a12
begin
for(i4=0;i4<2;i4=i4+1)//a11
begin
for(i5=0;i5<2;i5=i5+1)//a10
begin
for(i6=0;i6<2;i6=i6+1)//a9
begin
for(i7=0;i7<2;i7=i7+1)//a8
begin
for(i8=0;i8<2;i8=i8+1) //a7
begin
for(i9=0;i9<2;i9=i9+1) //a6
begin
for(i10=0;i10<2;i10=i10+1) //a5
begin
for(i11=0;i11<2;i11=i11+1) //a4
begin
for(i12=0;i12<2;i12=i12+1) //a3
begin
for(i13=0;i13<2;i13=i13+1) //a2
begin
for(i14=0;i14<2;i14=i14+1) //a1
begin
for(i15=0;i15<2;i15=i15+1) //a0
begin
for(j0=0;j0<2;j0=j0+1) //b15
begin
for(j1=0;j1<2;j1=j1+1)//b14
begin
for(j2=0;j2<2;j2=j2+1) //b13
begin
for(j3=0;j3<2;j3=j3+1)//b12
begin
for(j4=0;j4<2;j4=j4+1)//b11
begin
for(j5=0;j5<2;j5=j5+1)//b10
begin
for(j6=0;j6<2;j6=j6+1)//b9
begin
for(j7=0;j7<2;j7=j7+1)//b8
begin
for(j8=0;j8<2;j8=j8+1)//b7
begin
for(j9=0;j9<2;j9=j9+1)//b6
begin
for(j10=0;j10<2;j10=j10+1)//b5
begin
for(j11=0;j11<2;j11=j11+1)//b4
begin
for(j12=0;j12<2;j12=j12+1)//b3
begin
for(j13=0;j13<2;j13=j13+1)//b2
begin
for(j14=0;j14<2;j14=j14+1)//b1
begin
for(j15=0;j15<2;j15=j15+1)//b0
begin
b[0] = b[0] + 1'b1; #10;
end
b[1] = b[1] + 1'b1;
end
b[2] = b[2] + 1'b1;
end
b[3] = b[3] + 1'b1;
end
b[4] = b[4] + 1'b1;
end
b[5] = b[5] + 1'b1;
end
b[6] = b[6] + 1'b1;
end
b[7] = b[7] + 1'b1;
end
b[8] = b[8] + 1'b1;
end
b[9] = b[9] + 1'b1;
end
b[10] = b[10] + 1'b1;
end
b[11] = b[11] + 1'b1;
end
b[12] = b[12] + 1'b1;
end
b[13] = b[13] + 1'b1;
end
b[14] = b[14] + 1'b1;
end
b[15] = b[15] + 1'b1;
end
a[0] = a[0] + 1'b1;
end
a[1] = a[1] + 1'b1;
end
a[2] = a[2] + 1'b1;
end
a[3] = a[3]+ 1'b1;
end
a[4] = a[4] + 1'b1;
end
a[5] = a[5] + 1'b1;
end
a[6] = a[6] + 1'b1;
end
a[7] = a[7] + 1'b1;
end
a[8] = a[8] + 1'b1;
end
a[9] = a[9] + 1'b1;
end
a[10] = a[10] + 1'b1;
end
a[11] = a[11] + 1'b1;
end
a[12] = a[12] + 1'b1;
end
a[13] = a[13] + 1'b1;
end
a[14] = a[14] + 1'b1;
end
a[15]= a[15] + 1'b1;
end
end
endmodule
答案 0 :(得分：0)
首先，您认为您的代码具有可读性和可维护性吗？
第二，可以使用乘法运算符而不是嵌套循环来完成乘法。除乘法算法外，还有2个1位加法的嵌套循环。我不知道您的算法如何使用这么多嵌套循环并进行乘法...
传播延迟是通过静态时序分析（STA）计算的。 STA需要有关您电路的时序信息。最简单的方法是指定时钟并注册所有输入和输出。这将为您计算FF到FF的延迟路径。