是否可以根据参数的值在Verilog中创建条件硬件?像这样
module test #(
parameter param = 1
)(
input wire clk
);
reg[3:0] counter = 0;
always @(posedge clk) begin
`ifdef (param == 0) // <-----
counter <= counter + 1'b1;
// ... more hardware here
`else
counter <= counter - 1'b1;
// ... a different hardware here
`endif
end
endmodule // test
编辑:
答案 0 :(得分:1)
是的,您可以调整参数。就像在其他条件上一样使用它们(尽管您也可以在程序块之外使用它们来对整个实例进行条件化):
module test #(parameter param = 1)
(
input wire clk
);
reg[3:0] counter = 0;
always @(posedge clk) begin
if (param == 0) begin
counter <= counter + 1'b1;
end
else begin
counter <= counter - 1'b1;
end
end
endmodule // test
答案 1 :(得分:0)
实际上有generate
个块是出于这个原因而发明的:
module test
#(parameter param = 1)
(input wire clk);
reg [3:0] counter = 0;
generate
if (param == 0)
always @(posedge clk) begin
counter <= counter + 1'b1;
// ... more hardware here
end
else
always @(posedge clk) begin
counter <= counter - 1'b1;
// ... a different hardware here
end
endgenerate
endmodule // test