基于参数值的Verilog条件硬件

时间:2018-08-28 15:26:27

标签: verilog conditional-compilation

是否可以根据参数的值在Verilog中创建条件硬件?像这样

module test #(
 parameter param = 1
)(
  input wire clk
);

reg[3:0] counter = 0;

always @(posedge clk) begin
  `ifdef (param == 0)          // <-----
    counter <= counter + 1'b1;
    // ... more hardware here
  `else
    counter <= counter - 1'b1;
    // ... a different hardware here
  `endif
end

endmodule // test

编辑:

我想提到SergeUnn给出的答案都为我所寻找的实现提供了解决方案。有关更多详细信息,请参见答案的注释。

2 个答案:

答案 0 :(得分:1)

是的,您可以调整参数。就像在其他条件上一样使用它们(尽管您也可以在程序块之外使用它们来对整个实例进行条件化):

module test #(parameter param = 1)
  (
  input wire clk
  );

  reg[3:0] counter = 0;

  always @(posedge clk) begin
    if (param == 0) begin
      counter <= counter + 1'b1;
    end
    else begin
      counter <= counter - 1'b1;
    end
  end

endmodule // test

答案 1 :(得分:0)

实际上有generate个块是出于这个原因而发明的:

module test 
  #(parameter param = 1)
   (input wire clk);

   reg [3:0]  counter = 0;

   generate
      if (param == 0) 
        always @(posedge clk) begin
           counter <= counter + 1'b1;
           // ... more hardware here
        end
      else
        always @(posedge clk) begin
           counter <= counter - 1'b1;
           // ... a different hardware here
        end
   endgenerate
endmodule // test