SystemVerilog封面组包括基于参数的封面

时间:2019-01-10 22:38:10

标签: system-verilog

我正在为我的设计创建coverage,我想为多个实例重用covergroup定义。第一个实例应按预期使用所有coverpoint,但对于第二个实例,我要排除covergroup中的某些coverpoint。

我当时想我可以使用覆盖组的输入,并且iff()不需要的覆盖点,这样第一个实例将输入绑定为1,第二个实例将输入绑定为0。但是,我认为这仍然会显示覆盖点对于第二个实例,总是不会被选中,所以我希望它们完全不被包含。

covergroup cg_address(input bit enable) @ (posedge clock);
    address_check: coverpoint (address){
        bins addr_0 = {5'd0};
        bins addr_1 = {5'd1};
    }
    data_check: coverpoint (data) iff (enable){
        bins data_0 = {10'd0};
        bins data_1 = {10'd1};
    }
endgroup : cg_address

cg_address cg_address_inst0 = new(1'b1);
cg_address cg_address_inst1 = new(1'b0); //want this one to exclude data_check coverpoint

我知道上面的代码将不起作用,因为第二个实例仍将具有data_check覆盖点,因为启用已绑定到0,所以它将永远不会命中任何一个bin。还有其他方法可以尝试排除data_check吗?第二例的掩护点?

1 个答案:

答案 0 :(得分:2)

您需要做两件事:

  1. 将覆盖点的权重设置为0。
  2. 打开封面的option.per_instance = 1;

例如:

covergroup cg_address(input bit enable) @ (posedge clock);
    option.per_instance = 1;
    address_check: coverpoint (address){
        bins addr_0 = {5'd0};
        bins addr_1 = {5'd1};
    }
    data_check: coverpoint (data) {
        option.weight = enable;
        bins data_0 = {10'd0};
        bins data_1 = {10'd1};
    }
endgroup : cg_address

cg_address cg_address_inst0 = new(1);
cg_address cg_address_inst1 = new(0); //want this one to exclude data_check coverpoint