如何通过clk在vhdl中逐行读取文本文件?

时间:2018-07-17 16:30:22

标签: vhdl

我正在尝试在时钟事件中逐行读取文本文件以输出。但是我的代码在每个时钟中仅读取第一个元素!问题出在哪里?

FROM

myFile.txt:

entity filter_tb is
PORT( clk : IN std_logic;   
     filter_out : OUT real 
     );
end filter_tb;

architecture filter_tb of filter_tb is
begin

process(clk) 
    file file_pointer : text;
    variable line_content : real;
    variable line_num : line; 
begin
    file_open(file_pointer,"myFile.txt",READ_MODE);
    readline(file_pointer, line_num); 
    read(line_num, line_content);
    filter_out <= line_content;
    file_close(file_pointer);
end process;

end filter_tb;

2 个答案:

答案 0 :(得分:1)

您将在每个clk上重新打开和关闭文件。

在此过程中,{{1}中的wait untilrising_edge中的(clk)发生了。保持文件打开

entity filter_tb is
PORT( clk : IN std_logic;   
     filter_out : OUT real 
     );
end filter_tb;

architecture filter_tb of filter_tb is
begin

process 
    file file_pointer : text;
    variable line_content : real;
    variable line_num : line; 
begin
    file_open(file_pointer,"myFile.txt",READ_MODE);
    while not endfile(file_pointer) loop
        readline(file_pointer, line_num); 
        read(line_num, line_content);
        filter_out <= line_content;
        wait until rising_edge(clk);
    end loop;
    file_close(file_pointer);
    wait;
end process;

end filter_tb;

答案 1 :(得分:1)

不是一个Minimal Complete and Verifiable example,缺少根声明区域中的一些context子句元素以及使用设计模型的方法:

<table>
    <tbody>
    <!-- <template v-for="(datarow, i) in dataset"> does not work IE11 -->
    <tr v-for="(datarow, i) in dataset">
        <td>{{ datarow.firstname }}</td>
        <td>{{ datarow.lastname }}</td>
        <td>{{ datarow.email }}</td>
    </tr>
    <!-- I need the following every say 25 rows:
        <tr v-if="!(i % 25)"> //note it must be inside the same loop where `i` is declared though..
        <td>First</td> <td>Last</td> <td>Email</td>
        </tr>
        </template>
        -->
    </tbody>
</table>

您只需要打开和关闭文件一次。阶段如下:打开文件,每个时钟读取一次数据,如果没有更多数据关闭文件,则暂停该过程,直到模拟结束。

library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;

entity filter_tb is

这使用了一个不同的file_open过程调用,该过程还会在报告时使您明显地重复打开文件时分​​配一个file_open_status变量。

没有更多行可读取后,文件将关闭。请注意,loop语句中的wait语句在时钟边缘事件上等待,每个时钟将读取一个数据。

最后的等待语句会在其余的模拟过程中暂停该过程。

使用顶级端口,我们可以添加一个封闭的测试台:

architecture filter_tb of filter_tb is
begin

    process -- (clk)            -- process now contains wait statement
        constant filename:      string := "myFile.txt"; -- use more than once
        file file_pointer:      text;
        variable line_content:  real;
        variable line_num:      line; 
        variable filestatus:    file_open_status;
    begin
        file_open (filestatus, file_pointer, filename, READ_MODE);
        report filename & LF & HT & "file_open_status = " & 
                    file_open_status'image(filestatus);
        assert filestatus = OPEN_OK 
            report "file_open_status /= file_ok"
            severity FAILURE;    -- end simulation

        while not ENDFILE (file_pointer) loop
            wait until falling_edge(clk);  -- once per clock
            readline (file_pointer, line_num); 
            read (line_num, line_content);
            filter_out <= line_content;
        end loop;

        wait until falling_edge(clk); -- the last datum can be used first
        file_close (file_pointer);
        report filename & " closed.";
        wait;

    end process;

end architecture filter_tb;

监视进程可以在每个活动时钟沿上报告filter_out的值:

library ieee;
use ieee.std_logic_1164.all;

entity tb_filter_tb is
end entity;

architecture foo of tb_filter_tb is
    signal clk:         std_logic := '0';
    signal filter_out:  real;
begin
DUT:
    entity work.filter_tb
        port map (
            clk => clk,
            filter_out => filter_out
        );

CLOCK:
    process
    begin
        wait for 5 ns;
        clk <= not clk;
        if now > 90 ns then
            wait;
        end if;
    end process;
MONITOR:
    process
    begin
        wait until falling_edge(clk);
        wait for 0 ns;
        report "filter_out = " & real'image(filter_out);
    end process;
end architecture;

直到模拟结束。