CLK在VHDL中实现计数器的问题

Question

我正在尝试实现计数器，该计数器给出的输出值为1到6，我想稍后将其放在fpga的7段显示中。问题出在CLK上，process看不到CLK的值发生变化，并且模拟始终将输出值设置为“ 1001111”。

library ieee;
use ieee.std_logic_1164.all;

entity projekt is
    generic ( half_period : time := 10ms);
    port(Q : out std_logic_vector(6 downto 0));
end projekt;

architecture a1 of projekt is
    signal CLK : std_logic := '0';
begin
    CLK <= not CLK after half_period;
    process(CLK)
        variable tmpQ : integer range 0 to 7 := 1;
    begin
        if ( CLK = '1' and CLK'event ) then
            tmpQ := tmpQ + 1;
            if tmpQ = 7 then
                tmpQ := 1;
            end if;
        end if;
        case tmpQ is
            when 1 => Q <= "1001111";
            when 2 => Q <= "0010010";
            when 3 => Q <= "0000110";
            when 4 => Q <= "1001100";
            when 5 => Q <= "0100100";
            when 6 => Q <= "0100000";
            when others => Q <= "1111111";
        end case;
    end process;
end a1;

是否在if语句中CLK不变或程序从不进入？