Question

我正在尝试模拟VHDL项目，而modelsim给出了以下错误：

> Error: (vsim-3173) Entity 'C:/Users/arco.DESKTOP-KBU8HF2/Desktop/ALL/facul/circuitos/Nova pasta/simulation/modelsim/rtl_work.relogio' has no architecture.

我正在运行Quartus Prime Lite Edition 16.0和Modelsim 10.5b。这是我的代码：

library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity Relogio is port(
    clk,enable,clear: in std_logic;
    HEX1: out std_logic_vector(3 downto 0);
    HEX2: out std_logic_vector(3 downto 0);
    max: out std_logic);
end Relogio;

architecture behvRelogio of Relogio is


    component Clock_50 is port(
        clk,enable,clear: in std_logic;
        S: out std_logic_vector(25 downto 0);
        max: out std_logic);
    end component;

    component unidadeSegundos is port(
        clk,enable,clear: in std_logic;
        S: out std_logic_vector(3 downto 0);
        max: out std_logic);
    end component;

    component dezenaSegundos is port(
        clk,enable,clear: in std_logic;
        S: out std_logic_vector(3 downto 0);
        max: out std_logic);
    end component;

    signal CLOCK: std_logic;
    signal m: std_logic;

    begin

        CLK1: Clock_50 port map(clk,enable,clear,open,CLOCK);
        US: unidadeSegundos port map(clk,(enable and CLOCK),clear,HEX1(3 downto 0),m);
        DS: dezenaSegundos port map(clk,(m and CLOCK),clear,HEX2(3 downto 0),open);
    end behvRelogio;

Modelsim“实体'......'没有架构。”错误

0 个答案: