Question

我试图模拟VHDL项目，但modelsim给出了以下错误消息：

#include <stdio.h>

typedef struct point { int x, y; } Point;

void rotate(int n, char array[n][n]){
    //rotate right 90 degrees
    if(n == 1) return ;
    int times = n / 2;
    for(int i = 0; i < times; ++i){
        Point base = { i, i };
        for(int j = 0; j < n - 1; ++j){
            Point transition[4] = { {j, n-1}, {n-1,n-1-j},{n-1-j,0},{0,j} };
            char curr = array[base.x][base.y+j];//base + {0,j}
            for(int k = 0; k < 4; ++k){
                char temp = array[base.x + transition[k].x][base.y + transition[k].y];
                array[base.x + transition[k].x][base.y + transition[k].y] = curr;
                curr = temp;
            }
        }
        n -= 2;
    }
}

void display(int n, char array[n][n]){
    for(int i = 0; i < n; ++i){
        for(int j = 0; j < n; ++j){
            if(j)
                putchar(' ');
            putchar(array[i][j]);
        }
        putchar('\n');
    }
    putchar('\n');
}

int main(void){
    //demo
    char array4[4][4] = {
        {'1','2','3','4'},
        {'5','6','7','8'},
        {'9','A','B','C'},
        {'D','E','F','0'}
    };
    display(4, array4);
    int n = 4;
    while(n--){
        rotate(4, array4);
        display(4, array4);
    }
    char array5[5][5] = {
        {'A','B','C','D','E'},
        {'F','G','H','I','J'},
        {'K','L','M','N','O'},
        {'P','Q','R','S','T'},
        {'U','V','W','X','Y'}
    };
    display(5, array5);
    n = 4;
    while(n--){
        rotate(5, array5);
        display(5, array5);
    }
}

我尝试了另一个项目的creatindg，它给了我同样的错误。之前我能够模拟其他项目，做同样的事情。

我正在运行Quartus Prime Lite Edition 16.0和Modelsim 10.5b。我试图模拟的代码是：

Error: (vsim-3173) Entity 'C:/Users/chose/Documents/CTD/teste/SELETORES/simulation/modelsim/rtl_work.seletores' has no architecture.

Answer 1

首先，在L2组件实例化中存在一些语法错误。其次，在我看来，这是正确的方法（在端口映射中不允许运营商）：

library IEEE;
use IEEE.std_logic_1164.all;

entity SELETORES is
port(   IN_POT: in std_logic;
        OUT_POT, REG_ALARM, REG_OPEN, CONTA, SW
                :   in  std_logic_vector(9 downto 0);
        MODE    :   in  std_logic_vector(39 downto 0);
        SEL_DISP, SEL_LED
                :   in      std_logic_vector(1 downto 0);
        LED_OUT, SEL_TIME, SEL_POT
                :   out std_logic_vector(9 downto 0);
        REG :   out std_logic_vector(19 downto 0)
        );
end SELETORES;

architecture SELETORES_bhv of SELETORES is

-- Component declarations

component mux_4x1_20
  port (W,X,Y,Z: in std_logic_vector(19 downto 0);
        S1: in std_logic_vector(1 downto 0);
        F: out std_logic_vector(19 downto 0)
        );
end component;

component mux_4x1_10
  port (W,X,Y,Z: in std_logic_vector(9 downto 0);
        S2: in std_logic_vector(1 downto 0);
        F: out std_logic_vector(9 downto 0)
        );
end component;

component mux_2x1
  port (W,X: in std_logic_vector(9 downto 0);
        S3: in std_logic;
        F: out std_logic_vector(9 downto 0)
        );
end component;

component decod_time
  port(ENTRADA : in    std_logic_vector(9 downto 0);
       SAIDA: out  std_logic_vector(19 downto 0)
       );
end component;

--End component declarations

-- Internal signals

signal decod_mux : std_logic_vector(19 downto 0);
signal foobar: std_logic;

--End Internal Signals

begin

foobar <= SEL_DISP(0) AND NOT SEL_DISP(1);

L1 : mux_4x1_10 port map ("0000000000", REG_OPEN, OUT_POT, REG_ALARM, SEL_LED, LED_OUT);

L2 : mux_2x1 port map (SW, MODE(19 downto 10), foobar, SEL_TIME);

L3 : decod_time port map (CONTA, decod_mux);

L4 : mux_4x1_20 port map ("00000110010111101111", MODE(39 downto 20), decod_mux, "11111100011100111101", SEL_DISP, REG);

L5 : mux_2x1 port map (SW, MODE(9 downto 0), IN_POT, SEL_POT);

end SELETORES_bhv;

我在ModelSim 10.1c上测试过没有问题。

Modelsim＆＃34;实体＆＃39; ...＆＃39;没有建筑。＆＃34;错误

1 个答案: