发布verilog计数器不减少

Question

我是学生，学习verilog编程。首先，我尝试编写一个简单的程序。程序的意图很简单。对于第一个周期，我的输出必须与输入和前进相同，如果输入为1，输出必须为1一段时间，然后必须切换，输出必须是同一时间。我尝试编写编程但看起来总是得到1作为输出。你能帮我理解一下这个问题吗？请在下面找到我的计划。

`timescale 1ns / 1ps

module wave(input wire clk, inp,
            output wire ot, t,
            output reg tick);
  localparam [1:0] s1=2'b00, s2=2'b01, s3=2'b10, s4=2'b11;

  reg [1:0] state_r, state_n;
  reg [9:0] delay_r, delay_n;
  reg out_n, out_r;
  reg initial_count;
  reg input_n;
  wire CLK;

  clk clkk(.clk_in(clk), .clk_out(CLK), .tick(), .y());

  initial begin
    state_n=s1;
    delay_n=600;
    out_r=0;
    initial_count=0;
    input_n=0;
  end

  always @(posedge CLK) begin
    //delay_r<=600;
    //out_r<=out_n;
    //state_r<=state_n;
  end

  always @* begin
    case(state_n)
    s1: if (initial_count==0) begin
      out_n = inp;
      initial_count = 1;
      state_n = s1;
    end
    else if (inp==0) begin
      delay_r = 600;
      out_n = 0;
      state_n = s3;
    end
    else if (inp==1) begin
      delay_r = 600;
      out_n = 1;
      state_n = s2;
    end
    s2: if (delay_r>0) begin
      out_n = 1;
      delay_r = delay_r-1;
      state_n = s2;
    end
    else begin
      tick = 1;
      out_n = 0;
      delay_r = 600;
      state_n = s3;
    end
//  else
        //begin
            //state_n=s2;
        //end
    s3:if (delay_r>0) begin
      out_n = 0;
      delay_r = delay_r-1;
      state_n = s3;
    end
    else if (inp==1) begin
      out_n = 1;
      tick = 1;
      input_n = 1;
      delay_r = 600;
      state_n = s2;
    end
    else begin
      out_n = 0;
      state_n = s3;
    end
    endcase
  end

  assign ot = out_n;
  assign t = tick;
endmodule


/////clk generation

module clk(input wire clk_in,
           output wire clk_out,
           output reg [2:0] y,
           output wire tick);
  reg tick1;
  reg clk_out1;

  initial begin 
    y = 0;
    clk_out1 = 0;
    tick1 = 1'b0;
  end

  always @(posedge clk_in) begin
    y = y+1;
    if (y==2) begin
        clk_out1 = ~clk_out1;
        tick1 = 1'b1;
        y = 0;
    end
    else
      tick1 = 1'b0;
  end

  assign clk_out = clk_out1;
  assign tick = tick1;
endmodule

测试台代码

always
begin
clk=1'b0;
#10;
clk=1'b1;
#10;
end
always
begin
    // Initialize Inputs
    //clk = 0;
    //inp = 0;

    // Wait 100 ns for global reset to finish
    //#10000;
    inp = 1;

    // Wait 100 ns for global reset to finish
    #10000;
    inp = 0;

    // Wait 100 ns for global reset to finish
    #10000;
    inp = 1;

    // Wait 100 ns for global reset to finish
    #10000;
    inp = 0;

    // Wait 100 ns for global reset to finish
    #10000;
    inp = 1;

    // Wait 100 ns for global reset to finish
    #10000;
    inp = 0;

    // Wait 100 ns for global reset to finish
    #10000;

    // Add stimulus here

end