Question

我创建了以下fsm来控制一个fir过滤器，但是我在编译时遇到了两个错误。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;

entity fsm is
generic (n: integer:=4);
port( clk: in STD_LOGIC;
        rst: in STD_LOGIC;
        a: out STD_LOGIC_VECTOR(2*n-1 downto 0));
end fsm;

architecture fsm_struct of fsm is
type state_type is (state0, state1, state2);
signal state: state_type;   

signal rstff, rom_enable, ram_read_enable, ram_write_enable: STD_LOGIC;




component filter_rom is
    generic (n: integer);
    port ( clk: in STD_LOGIC;
            rstff: in STD_LOGIC;
            rom_enable : in STD_LOGIC;
            ram_read_enable : in STD_LOGIC;
            ram_write_enable : in STD_LOGIC;
            a: out STD_LOGIC_VECTOR(2*n-1 downto 0));           
end component;


begin   



process(clk,rst)    
    variable delay1:integer:=0;
    variable delay2:integer:=0;
    variable delay3:integer:=0;
begin   
    if rst='1' then
        state<=state0;          
    else if rising_edge(clk) then

        case state is

            when state0 => --initialize & input data
                rom_enable<='1';
                rstff<='1'; 
                if delay1=1 then
                    rstff<='0';
                    state<=state1;
                    delay2:=0;
                else
                    delay1:=delay1+1;
                    state<=state0;
                end if;

            when state1 => --write data to ram
                if delay2=2 then
                    ram_write_enable<='1';
                    state<=state2;
                    delay3:=0;
                else
                    delay2:=delay2+1;
                    state<=state1;
                end if;


            when state2 => --read data from ram
                if delay3=1 then
                    ram_read_enable<='1';
                    state<=state0;
                    delay1:=0;
                else
                    delay3:=delay3+1;
                    state<=state2;
                end if;

        end case;
    end if;

end process;

filter0: filter_memory generic map(n=>n) port map(clk,rstff,rom_enable,ram_read_enable,ram_write_enable,a);

end fsm_struct;

我得到的错误是：第83行：“进程”附近的语法错误，第85行：“generic”附近的语法错误。在计划结束时。我知道我的代码甚至不会编译到你的任何机器，因为我的滤镜没有定义，但我需要一些新的眼睛帮助。

Answer 1

我使用了＆＃39;否则如果＆＃39;而不是＆＃39; elsif＆＃39;它没有编译。

Answer 2

filter0: filter_memory generic map(n=>n)但您的组件名称为filter_rom

尝试

filter0: filter_rom generic map(n=>n)

如果你改变其他，如果elsif也改变了它。

它在Vivado 2017.4中编译

VHDL FSM没有编译

2 个答案: