VHDL仿真无法生成输出

时间:2018-05-18 08:33:21

标签: vhdl simulation test-bench

我和一位同事正在研究一个课程项目,用VHDL计算N个数字的GCD(更大的公共分频器)。我们使用Euclid算法并编写了以下代码:

     P1: process(clk,rstN)
    begin
    if (rstn = '1') then
    CS <= redy;
        eqsig <= '0';
        x <= (others => '0');
        y <= (others => '0');
    elsif (clk'EVENT and clk = '1') then
        CS <= NS;  
   end if;
end process P1;


    P2: process(CS,eqsig,NS)
begin

    case CS is
        when redy =>
            NS <= inpt;
        when inpt =>
            NS <= comp;
        when comp =>
            if (eqsig = '1') then
                NS <= otpt;
            else 
                NS <= oper;
            end if;
        when oper =>
            NS <= comp;
        when otpt =>
            NS <= redy;
        when others =>
            NS <= redy;
    end case;
end process P2;

    P3: Process(CS,eqsig)
begin

    case CS is
        when oper =>
            if x<y then
            y <= y-x;
            elsif y<x then
            x <= x-y;
            end if;

        when comp =>
            if x=y then
                eqsig <= '1';
            else
                eqsig <= '0';
            end if;
       when otpt =>
           if (rden = '1') then
           rdata <= x;
           end if;
       when inpt =>
             if (wren'EVENT and wren = '1') then
                if (waddr = "00") then
                    x <= wdata;
              end if;
             end if;
             if (wren'EVENT and wren = '0') then
                 if (waddr = "01") then
                     y <= wdata;
               end if;
             end if;
        when others =>
            null;
    end case; 
end process P3;

当试图模拟它时,它表明输出是&#34; U&#34;虽然代码似乎没有错误,但它可以读取输入。这是测试平台:

rstN <= '0' after 10 ns;
        wren <= '1' after 10 ns, '0' after 70 ns;
        wdata <= "00000000000000000000000000000011" after 20 ns,
                 "00000000000000000000000000000110" after 60 ns;
        waddr <= "00"after 20 ns,
                 "01"after 60 ns;
        rden <= '1' after 90 ns;

clk_process : process
begin
    clk <= '0' ;
    wait for cp/2;
    clk <= '1';
    wait for cp/2;
end process;

非常感谢你。 BR //迪

0 个答案:

没有答案
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