Question

我可能不熟悉合成循环。我试图在VHDL中创建一个计数排序，它将整数数组的任意长度（比如N）作为排序的输入。设计代码很大程度上依赖于for循环。循环逻辑似乎在一个进程中是并行的，或者可能是跨进程的。所以我将所有的for循环放在一个进程中。但有了这个，循环似乎独立地并行执行。因为一个循环应该跟随另一个循环而失败了目的。

我使用了来自https://www.geeksforgeeks.org/counting-sort/

的计数排序算法

我无法使算法中提到的逻辑正常工作。 Q1 ：for循环如何在进程内执行。所有for循环是否并行执行。 Q2 ：在VHDL中是否有另一种方法为循环逻辑实现这一点，以便它以串行方式执行？ Q3 ：合成for循环有限制吗？

设计代码：

library ieee;
use ieee.std_logic_1164.all;

package sorting_pkg is
  type intarray is array(natural range <>) of std_logic_vector(7 downto 0);
end package;

library ieee;
use ieee.std_logic_1164.all; 
use work.sorting_pkg.all;
use IEEE.NUMERIC_STD.all;
use ieee.std_logic_unsigned.all;

entity Sorting is
    generic (
      N : integer );
    port( 
        --clk : in STD_LOGIC;
        rst : in STD_LOGIC;
        inStream : in intarray(0 to N-1);
        outStream : out intarray(0 to N-1);
        BoutArray: out intarray(0 to 16);
        CoutArray: out intarray(0 to 16)
    );
end entity;

architecture behavior of Sorting is
    signal BArray: intarray(0 to 16) := (others => "00000000");
    signal CArray: intarray(0 to 16) := (others => "00000000");
    signal DArray: intarray(0 to 16) := (others => "00000000");
    --signal Aindex1,Aindex2,Cindex,k: std_logic_vector(7 downto 0);
    --signal Aindex1,Aindex2,Cindex,k : natural range 0 to 16; 
begin
process
    begin 
    if(rst = '1') then
        outStream <=(others => "00000000");
    else
       Bloop: for i in 0 to N-1 loop
        BArray(to_integer(unsigned(inStream(i)))) <=BArray(to_integer(unsigned(inStream(i)))) + 1;
        end loop;
        CArray(0) <= BArray(0);
       Cloop: for j in 1 to 16 loop 
        CArray(j) <= BArray(j) + CArray(j - 1);
        end loop;
       Coutloop:for l in 0 to N-1 loop

        DArray(to_integer(unsigned(inStream(l)))) <= CArray(to_integer(unsigned(inStream(l)))) - 1;
        end loop;
        outloop:for m in 0 to N-1 loop
     outStream(to_integer(unsigned(DArray(to_integer(unsigned(inStream(m))))))) <= inStream(m); 
        end loop;
        BoutArray <= BArray;
        CoutArray <= DArray;
     end if;
     wait;


  end process;--end proc
end architecture;

Testbench代码：

library ieee;
use ieee.std_logic_1164.all;
library work; 
use work.sorting_pkg.all;
use IEEE.NUMERIC_STD.all;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity tb_camera is
--  Port ( );
end tb_camera;

architecture Behavioral of tb_camera is

component Sorting
    generic (
      N : integer := 10);
    PORT
        (--clk: in std_logic;
        rst : in std_logic;
        inStream : in intarray(0 to 9);
        outStream : out intarray(0 to 9);
        BoutArray: out intarray(0 to 16);
        CoutArray: out intarray(0 to 16)
                );
end component;

signal A : intarray(0 to 9);
signal D : intarray(0 to 9);
signal rst_tb       : std_logic;
-- signal clk_tb       : std_logic;
signal BoutArray       : intarray(0 to 16);
signal CoutArray       : intarray(0 to 16);
--constant clk_period : time :=500ns;

begin
    uut:Sorting port map (inStream => A, outStream => D, rst => rst_tb,
                           BoutArray => BoutArray, CoutArray=> CoutArray );


    sim_tb:process
        begin
            wait for 100ns;
            rst_tb<='1';
            wait for 100ns;
            rst_tb<='0';

            --wait for 50ns;
            A(0 to 9) <= (0 => x"07",
                          1 => x"09",
                          2 => x"06",
                          3 => x"02",
                          4 => x"05",
                          5 => x"00",
                          6 => x"08",
                          7 => x"01",
                          8 => x"03",
                          9 => x"04");
            wait;
            end process;
end Behavioral;

VHDL：多个for循环串行执行

0 个答案: