Question

我对带有组件的顺序逻辑感到困惑（我是新手）。我有这些组件，但是对于如何在流程中使用它们感到困惑。我需要帮助来了解顺序逻辑如何与组件配合使用，也不确定我的输入/输出向量是否正确。我在移位寄存器的输入和输出上遇到麻烦，例如x（0）<= sin是正确的调用。

我必须设计这个：（https://i.stack.imgur.com/mwVdw.jpg）

这是我的主文件

use IEEE.STD_LOGIC_1164.ALL;

entity sa_top is
  port( 
        x:      in STD_LOGIC_VECTOR(7 downto 0);
        y:      in STD_LOGIC_VECTOR(7 downto 0);
        clk:    in STD_LOGIC;
        rst:    in STD_LOGIC;
        s:      out STD_LOGIC_VECTOR(7 downto 0)
       );
end sa_top;

architecture Behavioral of sa_top is

-- shift register
component sr is
    port( 
          sin:  in STD_LOGIC;
          sout: out STD_LOGIC;
          clk:  in STD_LOGIC;
          rst:  in STD_LOGIC
         );
end component sr;

-- d flip/flop
component dff is 
    port( 
           d:   in STD_LOGIC;
           q:   in STD_LOGIC;
           clk: in STD_LOGIC;
           rst: in STD_LOGIC
           );
end component dff;

-- full adder
component fa is
    port( 
            a:     in STD_LOGIC;
            b:     in STD_LOGIC;
            cin:   in STD_LOGIC;
            sum:   out STD_LOGIC;
            cout:  out STD_LOGIC
         );
end component fa;

signal xi, yi, si: std_logic;
signal xo, yo, so: std_logic;


signal s_temp: std_logic;
signal carry: std_logic;

begin
xi <= x(0);
yi <= y(0);


inp_x_instance:  sr port map(sin => xi, sout => xo, clk => clk, rst => rst);
inp_y_instance:  sr port map(sin => yi, sout => yo, clk => clk, rst => rst);

adder_instace:   fa port map(a => xo, b=> yo, cin => carry, sum => si, cout => carry);

op_s_instance:   sr port map(sin => si, sout => so, clk => clk, rst => rst);

--df_instance: dff port map(d => s_temp, q => s_temp, clk => clk, rst => rst);

    process(clk, s_temp) is
    begin
        if rst = '1' then
            s <= (others=>'0');
        elsif rising_edge(clk) then
            s(0) <= so;
         end if;
    end process;
end Behavioral;```

Answer 1

我认为您所做的是正确的，唯一使您感到困惑的是实际的移位本身，您需要将其左移1位，再移至其他位。看起来像这样：

s(7 downto 1) <= s(6 downto 0);

所以最后一段代码应如下所示：（请注意，我已从进程的敏感度列表中删除了s_temp）

process(clk) is
begin
    if rst = '1' then
        s <= (others=>'0');
    elsif rising_edge(clk) then
        s(7 downto 1) <= s(6 downto 0);
        s(0) <= so;
     end if;
end process;

制作串行输入串行输出加法器

1 个答案: