以下代码包含vhdl文件和测试平台。
Main file
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lici is
port(PT_MSB : in std_logic_vector(31 downto 0);
PT_LSB: in std_logic_vector( 31 downto 0);
--key: in std_logic_vector(127 downto 0);
RK1: in std_logic_vector(31 downto 0);
RK2: in std_logic_vector(31 downto 0);
clk: in std_logic;
CT_LSB: out std_logic_vector(31 downto 0);
CT_MSB: out std_logic_vector(31 downto 0);
check: out std_logic_vector(31 downto 0)
);
end lici;
architecture beh of lici is
type S_BOX is array(15 downto 0)of std_logic_vector(3 downto 0);
signal sub: S_BOX:=(0=>x"3",1=>x"F",2=>x"E",3=>x"1",4=>x"0",5=>x"A",6=>x"5",7=>x"8",8=>x"c",9=>x"4",10=>x"B",11=>x"2",12=>x"9",13=>x"7",14=>x"6",15=>x"D");
begin
process(clk)
Variable var_PT_MSB : std_logic_vector(31 downto 0);
variable var_PT_LSB : std_logic_vector( 31 downto 0);
variable var_EN_PT_MSB: std_logic_vector(31 downto 0);
variable var_XOR_RK_SHR7: std_logic_vector(31 downto 0);
variable var_XOR_SHL3: std_logic_vector(31 downto 0);
variable var_CT_LSB: std_logic_vector(31 downto 0);
variable S_data: std_logic_vector(3 downto 0);
variable outside_counter: natural:= 0;
variable i: natural:= 1;
begin
var_PT_MSB:= PT_MSB;
var_PT_LSB:= PT_LSB;
if(outside_counter< 31) then
if(clk'event and clk='1' and i <= 8) then
S_data:= (var_PT_MSB(31 downto 28) and x"F");
case S_data is
when x"0"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(0);
when x"1"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(1);
when x"2"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(2);
when x"3"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(3);
when x"4"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(4);
when x"5"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(5);
when x"6"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(6);
when x"7"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(7);
when x"8"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(8);
when x"9"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(9);
when x"A"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(10);
when x"B"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(11);
when x"C"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(12);
when x"D"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(13);
when x"E"=> var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(14);
when others=>var_EN_PT_MSB(35-(i*4) downto 32-(i*4)):=sub(15);
end case;
var_PT_MSB:= std_logic_vector(shift_left(unsigned(var_PT_MSB),4));
i:=i+1;
end if;
var_XOR_SHL3:= var_EN_PT_MSB xor RK1 xor var_PT_LSB;
var_XOR_SHL3:= std_logic_vector(rotate_left(unsigned(var_XOR_SHL3),3));
var_XOR_RK_SHR7:= var_EN_PT_MSB xor RK2 xor var_XOR_SHL3;
CT_LSB<= std_logic_vector(rotate_right(unsigned(var_XOR_RK_SHR7),7));
var_CT_LSB:= std_logic_vector(rotate_right(unsigned(var_XOR_RK_SHR7),7));
CT_MSB<= var_XOR_SHL3;
var_PT_MSB:= var_XOR_SHL3;
var_PT_LSB:= var_CT_LSB;
check<= var_EN_PT_MSB;
outside_counter:= outside_counter+1;
end if;
end process;
end beh;
--------------------------------------------------------------------------
This is the test bench for it
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lici_tb is
end lici_tb;
architecture behav of lici_tb is
component lici is
port(PT_MSB : in std_logic_vector(31 downto 0);
PT_LSB: in std_logic_vector( 31 downto 0);
RK1: in std_logic_vector(31 downto 0);
RK2: in std_logic_vector(31 downto 0);
clk: in std_logic;
CT_LSB: out std_logic_vector (31 downto 0);
CT_MSB: out std_logic_vector(31 downto 0);
check: out std_logic_vector(31 downto 0)
);
end component;
signal clk :std_logic := '0';
signal PT_MSB:std_logic_vector(31 downto 0):=x"ABCDEF01";
signal PT_LSB:std_logic_vector( 31 downto 0):=x"23456789";
signal RK1:std_logic_vector(31 downto 0):=x"00000010";
signal RK2:std_logic_vector(31 downto 0):= x"00000001";
signal CT_LSB:std_logic_vector(31 downto 0);
signal CT_MSB: std_logic_vector(31 downto 0);
signal check: std_logic_vector(31 downto 0);
constant CLK_PERIOD : time := 10 ns;
begin
uut : lici port map (
PT_MSB => PT_MSB,
PT_LSB=>PT_LSB,
RK1=>RK1,
RK2=> RK2,
clk => clk,
CT_LSB=>CT_LSB,
CT_MSB => CT_MSB,
check=>check
);
Clk_process :process
begin
clk <= '0';
wait for CLK_PERIOD/2; --for half of clock period clk stays at '0'.
clk <= '1';
wait for CLK_PERIOD/2; --for next half of clock period clk stays at '1'.
end process;
end;
最后，我需要在CT_LSB和CT_MSB中有31个值。 在每个周期中，我希望在CT_LSB和CT_MSB中有不同的加密值， 在一个周期中，需要进行一次external_counter迭代，其中8 NIBBLE必须加密。 整个代码需要在不使用For循环的情况下工作。 有人可以帮我这个吗？