Question

我在Verilog中遇到累加器代码问题。我只是生成伪随机信号。然后，将随机信号电平-1从0更改为1，以便进行签名。后来，获得了acmin＆＃39;。在这一点上，我需要积累＆＃39; acmin＆＃39;信号。调试器没有给我任何错误，但我看不到任何结果。你能帮我找到问题吗？

module lfsr(clk, rst, seed, load, R, acc);
   input [3:0] R;
   input [26:0] seed;
   input load;
   input rst;
   input clk;
   reg [3:0]q;
   wire [3:0] S;
   wire overflow;
   wire [3:0] acmin ;
   wire [26:0] state_out;
   wire [26:0] state_in;
   output [7:0] acc;
   reg [7:0] acc;

   flipflop F[26:0] (state_out, clk, rst, state_in);
   mux M1[26:0] (state_in, load, seed, {state_out[25],state_out[24],state_out[23],state_out[22],state_out[21],state_out[20],state_out[19],state_out[18],state_out[17],state_out[16],state_out[15],state_out[14],state_out[13],state_out[12],state_out[11],state_out[10],state_out[9],state_out[8],state_out[7],state_out[6],state_out[5],state_out[4],state_out[3],state_out[2], state_out[1], state_out[0], nextbit});
   xor G1(nextbit, state_out[5], state_out[2], state_out[1], state_out[26]); 

   // Pseudorandom generator
   always@(clk) begin
      if (state_out[26]==0)  
         q=4'b1111;  // 0 to -1
      else
         q=4'b0001;  //1 to 1 
   end

   assign acmin= R*q; // accumulator input

   always@(clk) begin
      if(rst)
         acc = 8'b00000000;
      else
         acc = acc + acmin;
   end
endmodule

测试台;

module lfsrtst;
reg [3:0] R;
reg clk;
reg rst;
reg [26:0] seed;
reg load;
wire [7:0] acc;
lfsr lfsr(clk, rst, seed, load, R, acc);
initial
begin
clk = 0;
load = 0;
seed = 0;
rst = 0;
R=0;
#10 rst = 1;
#10 rst = 0;
#50 R = 4'b0111;
#50 R = 4'b0010;
#100 R = 4'b1111;
#50 R = 4'b1011;
#150 R = 4'b1101;
#50 R = 4'b1000;
end
// drive clock
always
#50 clk = !clk;
// program lfsr
initial begin
#100 seed = 27'b000000110000011000001000001;
load = 1;
#100 load = 0;
#1400 $stop;
end
endmodule

我有＆＃39; acmin＆＃39;如我所愿。我想积累“acmin＆＃39;每当时钟的边缘上升和下降时变量。但是，＆＃39; acc＆＃39;结果什么都没有，那么错误是什么？感谢。

Answer 1

我看到的主要问题是你有一个同步重置：

always@(clk) begin
  if(rst)
     acc = 8'b00000000;
  else
     acc = acc + acmin;
end

但是在你的测试平台中你只能选择重置＃20

#10 rst = 1;
#10 rst = 0;

这太短了，永远不会检测到重置。

如果延长这些延迟，则应解决问题。

#100 rst = 1;
#100 rst = 0;

// then later
// program lfsr
initial begin
   # also delay this so that it comes after the reset
   #300 seed = 27'b000000110000011000001000001;

或者你可以使重置异步。

always@(clk or posedge rst) begin

Answer 2

我会尝试通过添加posedge并转换为'＆lt; ='

来暗示触发器

always@(posedge clk) begin
  if(rst)
     acc <= 8'b00000000;
  else
     acc <= acc + acmin;
end

Verilog累积代码错误

2 个答案: