module encoder (op, in, clock, reset);
//$display("We are in initial procedural block");
input [15:0] in;
input clock, reset;
output [3:0] op;
wire [15:0] in;
wire clock, reset;
reg [3:0] op;
always @ ( posedge clock)
begin
$display("We are in initial procedural block");
if (reset)
begin
$display("we are in the reset condition");
op = 0;
end
else
begin
case(in)
16'h0002: #1 op = 4'b0001;
16'h0004: #1 op = 4'b0010;
16'h0008: #1 op = 4'b0011;
16'h0010: #1 op = 4'b0100;
16'h0012: #1 op = 4'b0101;
16'h0014: #1 op = 4'b0110;
16'h0018: #1 op = 4'b0111;
16'h0020: #1 op = 4'b1000;
16'h0022: #1 op = 4'b1001;
16'h0024: #1 op = 4'b1010;
16'h0028: #1 op = 4'b1011;
16'h0030: #1 op = 4'b1100;
16'h0032: #1 op = 4'b1101;
16'h0034: #1 op = 4'b1110;
16'h0038: #1 op = 4'b1111;
16'h0040: #1 op = 4'b0000;
default : $display("DEFAULT!!!");
endcase
end
end
endmodule
module encoder_tb;
input in, reset, clock;
output op;
reg [15:0] in = 16'h0000;
reg reset, clock;
wire [3:0] op;
//internal variable
reg [15:0] incremental_value = 16'h0002;
initial
begin
$monitor("time = %g,\tclock = %d,\tin = %h,\top = %b",
$time, reset, in, op );
$display("We are in initial procedural block");
in = 0;
reset = 0;
clock = 0;
op = 0;
#1 clock = !clock;
#10 reset = !reset;
#5 in = in + incremental_value;
#100 $finish;
end
always
begin
#1 clock = !clock;
#10 reset = !reset;
#5 in = in + incremental_value;
end
encoder_tb test_bench ( .op(op), .in(in), .clock(clock), .reset(reset) );
// Waveform Generation
initial
begin
$dumpfile("encoder.vcd");
$dumpvars(0,op,in,clock,reset);
end
endmodule
上面我试图为4位输出编码器创建一个16位输入。我能够编译我的代码没有任何错误，但在[iverilog encoder_tb.v -o encoder]＆amp; [vvp编码器vcd]命令它没有给我任何东西，即使我已经给了$ monitor和几个$ display陈述我能想到的地方。我试图找到错误，但由于我对此非常新，我无法调试此错误。任何和所有帮助表示赞赏。 谢谢。
答案 0 :(得分：0)
我的代码在2个不同的模拟器（VCS和Incisive）上出现编译错误。也许你的模拟器会编译代码，但由于编码不好而无法正常模拟。
encoder_tb模块包含input和output语句，但没有端口列表。
encoder_tb模块有自己的递归实例。
您对wire（op）进行了程序性分配。
当我进行这些更改时，我会得到一些输出：
module encoder (op, in, clock, reset);
//$display("We are in initial procedural block");
input [15:0] in;
input clock, reset;
output [3:0] op;
wire [15:0] in;
wire clock, reset;
reg [3:0] op;
always @ ( posedge clock)
begin
$display("We are in initial procedural block");
if (reset)
begin
$display("we are in the reset condition");
op = 0;
end
else
begin
case(in)
16'h0002: #1 op = 4'b0001;
16'h0004: #1 op = 4'b0010;
16'h0008: #1 op = 4'b0011;
16'h0010: #1 op = 4'b0100;
16'h0012: #1 op = 4'b0101;
16'h0014: #1 op = 4'b0110;
16'h0018: #1 op = 4'b0111;
16'h0020: #1 op = 4'b1000;
16'h0022: #1 op = 4'b1001;
16'h0024: #1 op = 4'b1010;
16'h0028: #1 op = 4'b1011;
16'h0030: #1 op = 4'b1100;
16'h0032: #1 op = 4'b1101;
16'h0034: #1 op = 4'b1110;
16'h0038: #1 op = 4'b1111;
16'h0040: #1 op = 4'b0000;
default : $display("DEFAULT!!!");
endcase
end
end
endmodule
module encoder_tb;
// input in, reset, clock;
// output op;
reg [15:0] in = 16'h0000;
reg reset, clock;
wire [3:0] op;
//internal variable
reg [15:0] incremental_value = 16'h0002;
initial
begin
$monitor("time = %g,\tclock = %d,\tin = %h,\top = %b",
$time, reset, in, op );
$display("We are in initial procedural block");
in = 0;
reset = 0;
clock = 0;
// op = 0;
#1 clock = !clock;
#10 reset = !reset;
#5 in = in + incremental_value;
#100 $finish;
end
always
begin
#1 clock = !clock;
#10 reset = !reset;
#5 in = in + incremental_value;
end
// encoder_tb test_bench ( .op(op), .in(in), .clock(clock), .reset(reset) );
encoder test_bench ( .op(op), .in(in), .clock(clock), .reset(reset) );
// Waveform Generation
initial
begin
$dumpfile("encoder.vcd");
$dumpvars(0,op,in,clock,reset);
end
endmodule
/*
We are in initial procedural block
time = 0, clock = 0, in = 0000, op = xxxx
We are in initial procedural block
DEFAULT!!!
time = 16, clock = 0, in = 0004, op = xxxx
We are in initial procedural block
time = 18, clock = 0, in = 0004, op = 0010
time = 27, clock = 1, in = 0004, op = 0010
time = 32, clock = 1, in = 0006, op = 0010
time = 43, clock = 0, in = 0006, op = 0010
time = 48, clock = 0, in = 0008, op = 0010
We are in initial procedural block
time = 50, clock = 0, in = 0008, op = 0011
time = 59, clock = 1, in = 0008, op = 0011
time = 64, clock = 1, in = 000a, op = 0011
time = 75, clock = 0, in = 000a, op = 0011
time = 80, clock = 0, in = 000c, op = 0011
We are in initial procedural block
DEFAULT!!!
time = 91, clock = 1, in = 000c, op = 0011
time = 96, clock = 1, in = 000e, op = 0011
time = 107, clock = 0, in = 000e, op = 0011
time = 112, clock = 0, in = 0010, op = 0011
We are in initial procedural block
time = 114, clock = 0, in = 0010, op = 0100
*/