这是我的累加器代码:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity akkumulator is
generic (N : natural:=1);
port(rst: in bit;
clk: in bit;
B : in natural range 0 to N-1;
A : out natural range 0 to N-1);
end akkumulator;
architecture verhalten of akkumulator is
begin
p1: process(rst, clk)
variable ergebnis : natural range 0 to N-1;
begin
if (rst = '1') then
ergebnis := 0;
elseif (clk'event and clk = '1') then
ergebnis := ergebnis + B;
end if;
A <= ergebnis;
end process;
end verhalten;
当我编译时,我收到以下错误消息:
**错误:C:/Modeltech_pe_edu_10.4a/examples/akkumulator.vhd(20):接近“then”:( vcom-1576)期待==或'+'或' - '或'&amp;'。
**错误:C:/Modeltech_pe_edu_10.4a/examples/akkumulator.vhd(25):VHDL编译器退出
为什么?