Question

我刚刚开始学习verilog，我正在尝试创建一个找到序列1010的mealy机器，所以我写了这个：

module Find1010(input clk, input in, output reg out);
    reg [1:0]st = 0;
    wire a = {st[0], in} == 2'b10;
    wire b = {st   , in} == 3'b101;
    always @(posedge clk)
    begin
        out  =   a & st[1];
        st   =  {a | b, in};
    end
endmodule

它工作但后来我更改了行wire a = {st[0], in} == 2'b10;

到wire a = st[0] & ~in;然后输出始终为0.为什么会发生这种情况？{st[0], in} == 2'b10和st[0] & ~in之间有什么区别？

这是我写的测试台：

module Test;
    reg in = 0, clk = 1;
    wire result;
    initial begin
         #4 in = 1;
         #4 in = 0;
         #2 in = 1;
         #2 in = 0;
         #2 in = 1;
         #2 in = 0;
         #2 in = 1;
         #4 in = 0;
         #2 in = 1;
         #2 in = 0;
         #3 $finish;
    end
    initial forever #1 clk = ~clk;
    always @(negedge clk)
        $display("Input: %b    Output: %b", in , result);
    Find1010 Mealy_Machine(
        .clk(clk),
        .in(in),
        .out(result)
    );
endmodule

Answer 1

没有区别（除非涉及X＆＃39;

）

问题是您的测试平台中存在竞争条件。您需要对9使用非阻止分配。或者更改时钟周期，因此in的更改不会落在时钟边缘。

Answer 2

两者都是一样的。

以下是相关的代码快照。

module temp ();
  reg a, b;
  wire c, d;

  assign c = ({a, b} == 2'b10);
  assign d = (a & ~b);

  always @ (a, b)
  begin
    $display("------");
    $display("a = %0b, b = %0b, c = %0b", a, b, c);
    $display("a = %0b, b = %0b, d = %0b", a, b, d);
  end

  initial
  begin
    a = 1'b0; b = 1'b0;
#1  a = 1'b0; b = 1'b1;
#1  a = 1'b0; b = 1'bz;
#1  a = 1'b0; b = 1'bx;
#1  a = 1'b1; b = 1'b0;
#1  a = 1'b1; b = 1'b1;
#1  a = 1'b1; b = 1'bz;
#1  a = 1'b1; b = 1'bx;
#1  a = 1'bx; b = 1'b0;
#1  a = 1'bx; b = 1'b1;
#1  a = 1'bx; b = 1'bz;
#1  a = 1'bx; b = 1'bx;
#1  a = 1'bz; b = 1'b0;
#1  a = 1'bz; b = 1'b1;
#1  a = 1'bz; b = 1'bz;
#1  a = 1'bz; b = 1'bx;
  end
endmodule

// Output - 
------
a = 0, b = 0, c = 0
a = 0, b = 0, d = 0
------
a = 0, b = 1, c = 0
a = 0, b = 1, d = 0
------
a = 0, b = z, c = 0
a = 0, b = z, d = 0
------
a = 0, b = x, c = 0
a = 0, b = x, d = 0
------
a = 1, b = 0, c = 1
a = 1, b = 0, d = 1
------
a = 1, b = 1, c = 0
a = 1, b = 1, d = 0
------
a = 1, b = z, c = x
a = 1, b = z, d = x
------
a = 1, b = x, c = x
a = 1, b = x, d = x
------
a = x, b = 0, c = x
a = x, b = 0, d = x
------
a = x, b = 1, c = 0
a = x, b = 1, d = 0
------
a = x, b = z, c = x
a = x, b = z, d = x
------
a = x, b = x, c = x
a = x, b = x, d = x
------
a = z, b = 0, c = x
a = z, b = 0, d = x
------
a = z, b = 1, c = 0
a = z, b = 1, d = 0
------
a = z, b = z, c = x
a = z, b = z, d = x
------
a = z, b = x, c = x
a = z, b = x, d = x
------

但是，如果您使用===，那么c＆amp;的输出会有所不同。 d。

原因是===也考虑了1'bx＆amp; 1'bz，而==没有。{/ p>
assign c = ({a, b} == 2'b10); assign d = (a & ~b); ------ a = 1, b = z, c = 0 a = 1, b = z, d = x

{a，b} == 2'b10和a＆amp;之间的差异~b在verilog中

2 个答案: